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Cadence Customers to Showcase Advanced Low-Power Designs at CDNLive!

Comments(0)Filed under: low-power, low power, MSV, CPF, mixed-signal, mixed signal, Common Power Format, power shutoff, power shut-off, low-power design, Sorin Dobre, advanced verification, body bias, CDNLive, CDNLive!CDNLive! Silicon Valley, taking place at the DoubleTree Hotel in San Jose, CA next week from March 13-14, 2012, brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing advanced silicon, SoCs, and systems. This year's theme is Connect, Share and Inspire.

There's a particularly strong showing this year for low power designs and techniques, with many user papers in Track 2, a shared track featuring Low Power and Mixed Signal. Track 2 low power papers are:

  • 9:00 Tuesday: A Comprehensive Approach to Verifying Low Power Mixed Signal Design using Conformal LP; Rambus Inc.
  • 9:00 Wednesday: Conformal Low Power - Complex Low Power Design Verification; Qualcomm Inc.
  • 10:00 Wednesday: Low Power Implementation on Freescale Kinetis Family; Freescale
  • 11:00 Wednesday: Low-Power Format CPF in Analog and Mixed-Signal Simulation and Macro IP Verification; Cadence

Those interested in mixed signal designs will benefit by staying with Track 2 for the duration, while for those interested in low power design and power optimization for purely digital designs could check out my personal picks from these other tracks:

Track 8 - High Performance
  • 1:30 Tuesday: Being Green - what Good Design and ccopt (formerly Azuro) can do to Reduce Power; Netronome Systems Inc.
  • 2:30 Tuesday: Mali-T604 Embedded General Purpose Computing for GPU implementation in CMOS32LP using Cadence Reference Methodology; ARM
  • 3:45 Tuesday: Implementation strategies for a high performance and low-power ARM® CortexTM-A15 processor: Methodology and tools usage best practices; Texas Instruments
  • 4:45 Tuesday: Improving Performance, Power and Area of a High Speed Dual-core ARM Cortex-A9 Processor with Clock Concurrent Optimization Technology; Broadcom
Track 4 - Verification
  • 3:45 Wednesday: Techtorial: Low Power Failures - What not to Plan; Cadence
  • 4:45 Wednesday: Low-power Verification using UVM SystemVerilog; Cadence
Of course, don't miss the keynote speeches from executives from ARM, TSMC and Cadence on Tuesday morning, and the Partner Expo on Tuesday evening. Go to CDNLive SV 2012 for more information.

See you there next week!

Pete Hardee 

 

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