At Cadence, we often get asked about various low-power design techniques: how well they work, what are the implementation and verification issues associated with them, and how effective they are at various process nodes. As a general trend we see aggressive power reduction techniques being adopted more widely as many designs, and by no means only mobile designs, become increasingly power-sensitive. But while many advanced techniques (which we take to be the ones applied to power domains, such as power shut-off, as opposed to well-established optimizations like clock gating) are clearly growing rapidly in adoption, some less well-known techniques only seem to find favor with a few, and it's less clear whether adoption is increasing.
In particular, it's widely believed that substrate biasing (AKA body biasing) gives a lesser return in more advanced process nodes (45/40, 32/28 and beyond). What's the latest we're hearing about this?
First the stats...
When we delivered live full-day low-power "Tech on Tour" symposiums around the world in late 2010 and early 2011, we met with over 500 designers interested in low power design. That gave us a great opportunity to survey them. Here's what we found for the adoption of low power technqiues: Biasing is currently used by 5% of our sample of designers, and expected near-future use is 17%. In comparison, for power shut-off, we found the technique in use by 51% currently and 68% in the near future. That would certainly imply the technique's adoption is growing.
Now the anecdotal evidence...
Here's what has been heard by a few of our low power experts worldwide when discussing biasing with customers:
- The top two reasons against using substrate biasing are bias supply routing congestion (which increases at more advanced nodes); and difficulty of generating all the bias supplies.
- Mobile device SoC's at advanced nodes need all the low-power techniques at the designer's disposal, including biasing, according to one major mobile SoC platform provider. Another provider sees their ability to widely-apply substrate biasing in their libraries and process as a significant differentiator.
- Some customers who do not apply biasing to the whole chip below 45/40nm instead apply the technique in conjunction with low voltage standby modes, especially in memories.
- At least one customer who used biasing successfully in a 90nm chip is applying biasing successfully to their next generation at 45nm, while another company using forward and reverse biasing in volume at 90nm struggled to meet timing in the next generation at 65nm.
Future of substrate biasing:
Substrate biasing is useful primarily to control leakage at near-threshold voltage in planar CMOS. When FinFET becomes the norm (already used in some 22/20nm processes and will become commonplace for the 14nm node), leakage is better controlled by the gate's 3-D topology and many experts believe use of substrate biasing is unlikely to offer further benefit.
Current support for substrate biasing in the Cadence Low-Power Solution:
Regardless of whether you believe substrate biasing is worth the effort, be assured that the technique is fully supported in Encounter Digital Implementation System and Conformal Low Power. However, please ensure it is also supported by your library provider and foundry.
If you have any experiences to share about substrate biasing or any thoughts on its future, we'd be happy to hear them!