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Low Power Design in 2011 and Predictions for 2012

Comments(0)Filed under: low-power, Hardee, low power, CPF, power analysis, Palladium, low-power design, FinFETs, Moore's Law', 2012 predictions, ESL, energy harvesting, DPA

It's that time of year again - winding down towards the end of the year, taking some time with the family, and looking forward to returning refreshed for a new year. So what was the big news for low power in 2011 and what do we have to look forward to in 2012?

It's sometimes humbling to look at one's own technology predictions and see how things fared a year or so further on. Sometime in 2010, I forget exactly when, I was on a "virtual panel" on an on-line technology conference. One of the questions was to comment on developments for future technologies in low power design. I offered the following three points:

  • 20nm node probably marks the end for continuing Moore's law on planar CMOS because process variability and leakage gets further out of control. What will emerge to enable 16/14nm node and keep Moore going? Will it be 3-D transistors, will SOI finally become economically viable, or will something else emerge?
  • Software is more and more influential on system power and we've got to move up the abstraction level to cope with that. New techniques in ESL power estimation and modeling will emerge
  • As application demands increase for mobile devices, and leakage becomes more of an issue even in standby modes, we will see the emergence of some energy harvesting techniques to compensate

Note that I was not necessarily saying we'd see all these within a year, but none-the-less, how did these predictions fare?

  • The end-of-the-line prediction for planar CMOS beyond 20nm was pretty good, as it turns out. What's even better news is that the leading emergent technology, fabricating transistors in 3-D which seems to be most popularly named FinFETs, looks like being very workable. So much so that Intel didn't wait for the 14/16nm node, but is already deploying the technology at 22nm (ref: http://www.nytimes.com/2011/05/05/science/05chip.html). Expected to be widely used at 14nm, FinFETs increase switching performance at reduced leakage, compared with planar CMOS, in a marvel of process technology engineering. This looks like it will have relatively little disruption on the current design tool flow, or current low power design techniques. Moore's Law looks good for a while yet.
  • As far as software's influence on power is concerned, real developments in ESL tools seemed few and far between. That's yet to happen and maybe we'll see progress in 2012. However, here at Cadence, we are witnessing greatly increasing usage of our Palladium Verification Computing Platform, with CPF support and the Dynamic Power Analysis (DPA) option, for executing the complete chip pre-silicon with software to both test the correct execution of power management (CPF) and estimate power in various real system modes (DPA). Not truly ESL you may argue, but getting the job done.
  • For energy harvesting, I thought we'd see much cleverer application of solar, thermal and mechanical harvesting in a wider range of mobile devices by now. Maybe we have been too good at deploying existing power management techniques to stretch battery life to at least a full day, to make the inclusion of such technologies in the device economically viable. We should start to see these emerging in the next few years, if not 2012, surely.

There you have it -- for what it's worth. I should mention that these predictions come with a money-back guarantee. If they fail to emerge as stated, I will happily refund exactly what you paid for them! Best wishes to you and yours for the Holidays and a happy and prosperous 2012.

Pete Hardee

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