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Low-power Keeps Gate-Level Simulation Forever Young

Comments(3)Filed under: low power, UPF, CPF, simulation, IES, verification, low-power design, IEEE 1801, shutdown, gate simulation, Ann Mutschler, gate-level simulation

Ann Mutschler blogged in the Low-Power Engineering Community that gate-level simulation is coming back, driven in part by low-power verification needs.  “In a small sense, what’s old is new” may actually be the biggest understatement in her blog.

Ann attributes the observation to Cadence’s Pete Hardee who sees low-power architectural and synchronization dependencies that require gate-level details for proper verification.  While gate simulation itself is an old general verification concept, the underlying need for accuracy has never gone out of style.  When most of the projects shifted to more synchronous designs in the middle and late 1990s, there was some talk about higher-level sign-off.  However, the increased integration of analog and low-power, especially where there are multiple clock domains, introduced new sources for asynchronous stimulus/response which required the accuracy of gate simulation to verify.

The understatement is that modern gate-level simulation is just driven by these new sources of asynchronicity. The reality is that low-power opens a whole new dimension of accuracy that Verilog (or VHDL/Vital) was never built to accommodate.  Truly accurate low-power simulation needs to model the shutdown corruption on domain inputs so that the simulation engine does not clear unknowns from the shutdown domain prematurely.  Another example is that the physical location of isolation and the delays on the isolation nets must be modeled to mimic silicon -- otherwise the simulator may not arrive at the right isolation values as it resolves the net values at a given point in time.  

On top of effects like these, Pete states the value of static formal checking.  However, it’s not just gate to RTL equivalence that is important -- gate simulation to implementation checking is also needed for the low-power modeling. So it’s not just a "small sense" that what’s old is new, but a significant new requirement that demands the accuracy only found in gate-level simulation to produce working silicon.

Have you recently found the need for more gate simulation?  If so, please share your experiences on what keeps gate simulation a key part of your verification process.

=Adam "low-power doesn't mean low-key" Sherer

 

Comments(3)

By Gaurav Jalan on September 15, 2011
A quick summary on the need for GLS  -
whatisverification.blogspot.com/.../gate-level-simulations-necessary-evil.html
whatisverification.blogspot.com/.../gate-level-simulations-necessary-evil_29.html
whatisverification.blogspot.com/.../gate-level-simulations-necessary-evil.html

By Adam Sherilog on September 15, 2011
Hi Gaurav,
Your blogs do provide a good background for gate-level simulation.  I would encourage you and your readers to explore the Incisive Enterprise Simulator as well.  Cadence invented most of the features you describe in your 3 posts.  In addition, we have several techniques to make the "necessary evils" you describe a lot less evil.  One of those is a great signal tracing capability in our own debugging tool SimVision.  Feel free to take a look at these links and blog about it on your WhatIsVerification.
www.cadence.com/.../23462.aspx
www.cadence.com/.../demo-new-signal-tracing-capability-in-incisive-enterprise-simulator.aspx
And with this one you could even add FSM mnemonics onto your traces to help with debug:
www.cadence.com/.../fsm-mnemonics-maps-enums-in-simvision-using-verilog-1364.aspx
We have many gate-level users at and below 40nm which leads us to innovate features that benefit all users.
=Adam

By Gaurav Jalan on October 9, 2012
Adam, apologies for being really late in replying. Missed your response. I have been an avid user of Incisive. Infact have seen the tool mature from 130nm till date :) The debugging capabilities are excellent!

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