Ann Mutschler blogged in the Low-Power Engineering Community that gate-level simulation is coming back, driven in part by low-power verification needs. “In a small sense, what’s old is new” may actually be the biggest understatement in her blog.
Ann attributes the observation to Cadence’s Pete Hardee who sees low-power architectural and synchronization dependencies that require gate-level details for proper verification. While gate simulation itself is an old general verification concept, the underlying need for accuracy has never gone out of style. When most of the projects shifted to more synchronous designs in the middle and late 1990s, there was some talk about higher-level sign-off. However, the increased integration of analog and low-power, especially where there are multiple clock domains, introduced new sources for asynchronous stimulus/response which required the accuracy of gate simulation to verify.
The understatement is that modern gate-level simulation is just driven by these new sources of asynchronicity. The reality is that low-power opens a whole new dimension of accuracy that Verilog (or VHDL/Vital) was never built to accommodate. Truly accurate low-power simulation needs to model the shutdown corruption on domain inputs so that the simulation engine does not clear unknowns from the shutdown domain prematurely. Another example is that the physical location of isolation and the delays on the isolation nets must be modeled to mimic silicon -- otherwise the simulator may not arrive at the right isolation values as it resolves the net values at a given point in time.
On top of effects like these, Pete states the value of static formal checking. However, it’s not just gate to RTL equivalence that is important -- gate simulation to implementation checking is also needed for the low-power modeling. So it’s not just a "small sense" that what’s old is new, but a significant new requirement that demands the accuracy only found in gate-level simulation to produce working silicon.
Have you recently found the need for more gate simulation? If so, please share your experiences on what keeps gate simulation a key part of your verification process.
=Adam "low-power doesn't mean low-key" Sherer