Home > Community > Blogs > Low Power > guc demonstrated how to do low power design at dac
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Low Power blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

GUC User Presentation at DAC: How to Do Low Power Design

Comments(0)Filed under: low power, PSO, CPF, DVFS, Common Power Format, DAC, Design Automation Conference, 28nm, Alex Kuo, Global Unichip, GUC, low-power design

Power was clearly a hot topic at the recent Design Automation Conference (DAC). Many companies demonstrated their unique tool capabilities to address power issues at different abstraction levels. However, we saw very few presentations that offered a user perspective on how they do low power designs and how EDA tools help. The presentation by Alex Kuo from Global Unichip Inc., at the EDA360 Theater in the Cadence booth, is one of the few exceptions.

Alex highlighted the importance of a good methodology for advanced low power designs. Particularly, he demonstrated how a Common Power  Format (CPF) enabled low power design flow helps GUC tape out designs on time using the most advanced low power design techniques, such as Power Shut-Off (PSO) and Dynamic Voltage Frequency Scaling (DVFS), and get first silicon right.

CPF is an open power intent standard from the Silicon Integration Initiative (Si2). According to Alex, CPF is used at GUC at every design stage to drive power exploration and estimation, low power functionality verification, and low power implementation. More importantly, Alex noted that he appreciated the comprehensiveness and maturity of the Cadence Low Power Solution, as all Cadence tools in this low power design flow support CPF and interpret the power intent consistently across all tools.

CPF-Enabled Low Power Design Flow (Source: Global Unichip Corp.)

When asked about the future of low power designs, Alex offered some interesting perspectives. In the past 4 years, GUC has taped out more than 100 low power designs at various technology nodes, from 90nm to 40nm, and they are working on 28nm now. As the industry moves to advanced nodes of 28nm and below, the process technology will help reduce power dissipation at the cell level.

However, due to the rapid increase in design complexity, the power density of the chip will become worse. As a result, Alex believes that a mature low power design methodology and comprehensive tool support will become more and more important for designing chips with maximized performance and the lowest energy consumption.

Qi Wang


Leave a Comment

E-mail (will not be published)
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.