The long awaited new version of the Common Power Format, CPF 2.0,
was released by the Silicon Integration Initiative (Si2), an industry standards
organization, today. Here are several interesting observations from
this latest release.
First of all, this new release is a big step forward for interoperability
between IEEE 1801 (Unified Power Format 2.0), the other industry power intent
format, and CPF. In 2009 the format working group of the Si2 Low Power Coalition
(LPC), which is responsible for maintaining CPF, released a document called Interoperability
Guide for Power Format Standards, which describes clearly how to map between an IEEE
1801 command/option to a CPF counterpart. It also shows which commands/options
of 1801 are declared as non-interoperable due to missing constructs in CPF and the
methodology differences between the two formats.
As a result, the LPC format group quickly started to work on the
extension of CPF to close the gaps identified by the interoperability guide.
According to the Si2 press release, the major improvements in this area include
the following, among many others:
The generic mode concept, which combines both power mode and
functional mode for a more comprehensive and robust power intent specification.
More flexible isolation and level shifter rule specification.
Link with the Liberty format for global supply net connection
based on pg_type attributes.
The release also has many important and useful extensions based on
the requirements from the member companies of the working group. For example, it
introduces a power design concept to enhance the hierarchal design flow. Also,
a new extension of simulation control adds significant flexibility for the user
control of simulation corruption semantics, especially on the non-synthesizable
behavioral constructs such as initial statements in Verilog.
In May 2010, after the Si2 LPC's call for technology contribution, Cadence made
a contribution to the extensions. Some of them were accepted by the format
working group. The contribution includes the enhancement of macro-models to
improve their usability for I/O pads, and support for analog/mixed-signal IP
with power management features. The Cadence contribution also includes extensions
to support some new types of low-power IP such as a special clamp cell, power
and ground level shifter, complex global cells, and isolation/level shifter
cells that can be placed anywhere in the design.
The CPF 2.0 specification acknowledges LPC Format working group
members, including representatives from Synopsys, Calypto, AMD, IBM, LSI, Si2,
and Cadence. Clearly, this shows the strong interest across the industry to
drive the CPF standard forward.
Cadence has been an active member of the format working group with
a strong commitment to supporting CPF in the tools and flows of the Cadence Low
Power Solution. The new CPF extension delivers the language support requested
by many of our customers who had successfully adopted a CPF based low power
design methodology. As a result, Cadence is committed to work with our key
technology partners to enhance our tools and flows based on the CPF 2.0 release
based on the priority requested by our customers.
In the next a few months we will run a series of blogs to dive
into some specific CPF 2.0 enhancements and to show how it can benefit