If you're like me, one of the things you appreciate about
traveling is the contrasts. It's great to experience the different cultures,
geography, architecture and cuisines across the world. It's the differences
that make it exciting. It was fun to experience those differences once again
as, for the first time in a while, I had a series of road trips taking me to
seven major cities across North America, Europe and Israel. Given the timing of
this trip, one of the biggest contrasts was crawling along an Autoroute in
heavy snow to an airport in France and only just making our plane in time, then
landing the same day in Tel Aviv where they were experiencing what still seemed
to be a Mediterranean summer! But on a technical level, it was the
similarities, not the differences, that I found more striking.
I was traveling with a couple of Cadence's low power experts
for a series of full-day seminars under the EDA360 Tech on Tour banner. These
were no marketing pitches to huge rooms of barely-interested engineers, but
much more intimate expert-to-expert discussions with smaller groups of
designers. We had plenty of time to interact with the attendees: we encouraged
the sessions to be interactive, we had breaks for informal discussion, and many
folks stayed around after to continue discussions over some suitable libations.
In case we missed anyone, we also had a simple yet focused survey questionnaire
to gauge where folks are at with their adoption of low power design techniques.
My first impression of the similarities was this: if there was a time when I
could characterize chip design in North America as being dominated by computing
and networks, Europe by wireless and automotive, and Israel by a dazzling array
of largely communications-focused start-ups, those times are gone. Such is the
convergence of applications, and shifting of the electronics markets to the
consumer, that the dual challenges of performance and power seemed to be
ubiquitous.
Based on the discussions and the interest in the various
aspects of low power design we were presenting, and the survey results, I can
broadly divide the 300 or so designers we met into three categories:
The newbies: Maybe
around 15-20% of the people we met were new designers in their companies who
wanted to get up to speed on advanced techniques that, in general, their
companies were already using.
The mainstream: This group was maybe about a half of the audiences on average -- experienced engineers
who now have an increased need to optimize for power and want to apply advanced
techniques, either to reduce power density or because their next designs are moving to
process nodes where they know leakage will be an issue.
The old hands: The
remaining one third or so of the folks we met already knew all of the advanced
techniques and had been using them for some time. They probably could have
given the presentations we were delivering just as capably, but luckily we had
an ace up our sleeve -- our team included a member of our Advanced Low Power
Services team who could talk about techniques so advanced that even this group
went away feeling they had learned something useful! Most, but not all, of this
group were working on devices for the mobile market.
Two more of the similarities were that first, that this audience
make-up did not significantly vary across the globe and second, we're starting
to see significant application of advanced low power techniques in non-mobile
(non-battery) applications.
By advanced low power techniques, I mean the ones that apply
to power domains -- splitting the design into separately-powered areas where the
voltage can be shut off to reduce leakage (Power Shut-Off -- PSO, aka State
Retention Power Gating -- SRPG) or supplied with different voltage levels (permanently
in the case of Multi-Supply Voltage -- MSV, or dynamically in the case of
Dynamic Voltage and Frequency Scaling -- DVFS). The basic techniques ("basic"
undersells them - there's actually a lot of good technology involved, but in
general they're well automated and do not have the impact on implementation,
verification and design closure that the "advanced" techniques do) include
clock gating and Multi-Threshold Voltage (MVt) optimization.
Given these definitions,
I can share one edited highlight of our survey results in the graph to the right.
Practically everyone is already using the basic techniques -- no real surprise
there, but over 60% are already using advanced techniques, a number which is
predicted to grow to a massive 95% on the next round of designs! Even given
that this was a Cadence seminar to customers interested in low power design, I
find that number interesting. A major part of this is the adoption of advanced low
power techniques beyond mobile equipment, mentioned earlier.
My conclusion: get on board! The advanced low power
revolution is in full swing!
Pete Hardee