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How Much Power is My Chip Really Using?

Comments(2)Filed under: low-power, power, low power, power-aware, power analysis, system power, clock tree

Today I'd like to dive into one of the topics I mentioned in my blog in August -- measuring chip power. This seems to be one of the questions I get from many people. How can a design team effectively measure power all throughout the design flow, with the key phrase being "throughout the entire flow"?

Power measurement requirements have evolved over the years from rough estimations to the need to have more precise power calculations. Because power specifications have become stricter, most design teams today can't treat power as a luxury, and just do the best they can towards the end of the flow. Power consumption today has to be gauged up front, worked towards during the design flow, and measured accurately at the end.

Still, there are many challenges to tackle. One of the main challenges is the lack of finalized design data early on in the flow. Let's look at the availability of quality design data throughout the flow:


As you can see, we do have quite a bit of information available at the project planning stage. However, most of this information is preliminary information. Can we get an accurate measurement on what the chip's final power consumption is going to be at this stage? Probably not. Can we get a good estimate? Absolutely! However, if anything changes in the project specs, it's important to propagate that to the estimate.

Next up is RTL and logic synthesis. In my opinion, the biggest "incomplete data" factor at this stage is the lack of physical optimization logic, and the clock network. For high random logic designs, the clock tree can consume up to 30% of total chip power, so this is actually a pretty big unknown at this point. Then, we have the RC difference between wireload and actual wires. All these factors can contribute to a significant difference, which is why synthesis-stage power calculations should be treated as a refined estimate at best. However, at this stage, you should already have an almost-finalized activity vector set -- at least one for average usage and one for peak power usage.

At design implementation we pretty much have most, if not all, of the design information needed. Indeed, at late stage design implementation (post-route), your power measurements should be spot-on with signoff, provided you are using the same activity vectors. Still, there are a few things that might derail your power measurement efforts. The most obvious two are: (1) the consistency of power models being used between implementation and signoff, especially for large macros, and (2) the consistency of the power calculation engine between implementation and signoff.

So, I've thrown out the main challenges of getting good power measurement at different stages of the design flow. Although these challenges may seem overwhelming at times, there are ways of overcoming or minimizing the risks associated with each of these challenges. Stay tuned for my next blog to find out what they are!

Wei-Lii Tan



By Ram Kumar on October 24, 2010
In Case of RTL compiler we have option called report power,if we give that command the tool generates Leackage,Net,Switching power so the question is In what condition tool generates that report
1. By Taking all the input conditions
2. Or Specific conditions
Can any one help this
Thank you for your patience.

By John Busco on November 1, 2010
How about correlating signoff power calculation vs. actual Silicon power consumption? What are the factors causing miscorrelation, and what are techniques to handle them?

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