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# Analog Coverage Metrics in Mixed-Signal Simulations

Comments(0)Filed under: thermal, low-power, low power, PSO, voltage, shutoff, MSV, AVS, CPF, DVFS, simulation, IR drop, LDO, adaptive, Dynamic power, scaling, RNM, PVT, wreal, frequency

This posting is part of a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I will cover metrics collection from analog circuits during mixed-signal simulation.

My previous blogs covered some of the following topics:

• 1. Basics of dynamic power management
• 2. Very brief introduction to RNM (Real Number Modeling) for efficient simulation of mixed signal SoCs
• 3. How to create a controlled voltage source using a Specman testbench
• 4. Closed-loop voltage scaling
• 5. Simulation of closed-loop adaptive voltage scaling
• 6. Error detection

Previous postings include:

Analog Coverage Model

Once the desired features of interest have been extracted from the spec and captured in an executable verification plan, the next step is to quantify the desired functionality that needs to be tested. This is typically done by designing a coverage model and collecting metrics from the analog elements in the design.

For maximum dynamic power savings, it is best to run the device at the lowest possible operating voltage. The device can function at any of the following operating nominal-voltages:

• On Nom-Voltage = 0.8 V (+/- 10%)
• On Nom-Voltage = 1.0 V (+/- 10%)
• On Nom-Voltage = 1.2 V (+/- 10%)
• On Nom-Voltage = 1.4 V (+/- 10%)
• On Nom-Voltage = 1.6 V (+/- 10%)
• Off Voltage (Powered Down)
• Illegal High Voltage

In our example, the effect of varying Vbat on Voltage regulation by the LDOs is carefully monitored, and voltage transitions are measured and assigned to voltage bins in the cover groups.

Figure 1: Mixed Signal Coverage Model

Figure 1 shows code for collecting functional coverage from the wreal models used in the prototype SoC. In this example, the battery voltage Vbat is binned into four categories. Vbat varies over different tests through predetermined ranges and sequences specified in the verification plan, and is kept track of to ensure all intended test conditions have been met. Figure 2 and Figure 3 show the cumulative results of the full regression run.

As the device is run through various tests, the output voltages from each LDO are carefully tracked. This gives us a good measure of the percentage of the time that each power domain in the device is run at lowest possible voltage, which has a direct correlation to the dynamic power actually being conserved. As seen in Figure 2, the MCU is successfully being run to conserve dynamic power - the higher the coverage data for the lowest nominal-voltage (0.8V), the more power that has been conserved. It is also important to ensure that all possible combinations of LDO voltages have been exercised for all possible legal Vbat values. This can be achieved by creating a cross product of Vbat with Vldo_mcu.

Figure 2: DMS - DVFS Coverage Data

Figure 3 shows the hole analysis run from the vPlan which in turn reveals that the DSP power domain was never run at the highest nominal voltage of 1.6V. Thus, this part of the plan has not been fully exercised and needs more tests to cover missing condition.

Similarly, holes in the verification space are seen in Figure 2.  These need to be filled by running adequate incremental tests to achieve functional closure.

Figure 3: Scaled Metrics in populated vPlan

In the next blog, I will talk about concepts behind DMSV - Digital-Centric Mixed Signal Verification.

Stay tuned for more...

Neyaz