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A Look Back On 2009 (Before Hazarding Predictions For 2010) - Functional Verification - Cadence Community

Fri, 29 Jan 2010 03:03:07 GMT

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Is this the David We ...

Anonymous — Wed, 30 Dec 2009 00:53:20 GMT

Is this the David Weir that worked for Motorolla in Australia?

This commnets help m ...

Anonymous — Tue, 15 Dec 2009 14:41:13 GMT

This commnets help me a lot. Thanks...

Hi Sudhir, the re ...

grasshopper — Sat, 05 Dec 2009 12:48:12 GMT

Hi Sudhir,

the recommended methodology in RC is to make all libraries available to the tool and let the tools take advantage of them and select the appropriate architectures for each block. library_domains can certainly be used for what you are asking but it is not the preferred methodology. In such an approach you would do something like

create_library_domain HP # high performance domain

create_library_domain LP # low power domain

set_attribute library_domain { LVT.lib } [find / -library_domain HP]

set_attribute library_domain { HVT.lib } [find / -library_domain LP]

and finally apply the corresponding domain to the appropriate blocks

As you can see, library_domains are a very powerful feature. The reason why it is not the favored flow is that this is saying that you can do a better job choosing the cells for the tool than the tool can do by itself. In doing so, you could involuntarily force the tool to pick different datapath architectures that may lead to HVT cells but much larger area so in the end you could have low performance and higher power if you are not careful. As you may imagine, I am not a big advocate of %LVT as a metric since it is not a real metric. User should look at real metrics like performance and overall power IMHO.

hope this helps

Diego, For leakag ...

Anonymous — Wed, 02 Dec 2009 04:57:47 GMT

Diego,

For leakage optimization, does RC have commands to force it to use lower VT cells for pre defined set of modules (which are timing critical) and use high VT cells for rest of the design?

There are a bunch of ...

Bob Loblaw — Wed, 04 Nov 2009 13:36:39 GMT

There are a bunch of differences, the first being that RC-Physical employs legal placement under the hood. And this includes its incremental placement, which is crucial as you do optimizations in synthesis based on the placement. And the incremental legal placement also enables you to hand off the placement at the end of synthesis, seeding the back-end flow with exactly the view of the design that you saw out of synthesis.

The other major difference is that RC-Physical has full capabilities for congestion analysis, fixing, and prevention. For more information on that, check out the archived webinar we recently did: www.cadence.com/.../event.aspx

Getting a blank scre ...

Colin Ng — Fri, 30 Oct 2009 12:27:38 GMT

Getting a blank screen in IE, when I clikc on "introduction".

please advice mw what does it take to start to view this material.

What is the major di ...

Henry Wang — Wed, 02 Sep 2009 09:37:27 GMT

What is the major difference between RCP and RC-Spatial?

Hi Sanjay, Thanks ...

Anonymous — Thu, 16 Jul 2009 18:12:48 GMT

Hi Sanjay,

Thanks for your feedback and sharing your experiences. I have also used all the tools you used before I joined Cadence as a designer. I agree with you, I've seen that if I didn't overconstrain using non-RC synthesis tools, my design sometimes wouldn't meet timing in the layout. It had been like that for a long time. However, whenever this overconstraining was needed, there was always a price, where it usually caused designs to blow up in size (my usual first care about for particular designs) if things are tight. I've seen so many designs grow because of overconstraining. Not just small growth, huge grow, as bad as 20-30% if you're not careful, because the tools works hard to make it work (I used to experiment with overconstraining to find the sweet spot for my synthesis tool for particular designs to meet my needs). What then happened was that the backend designer told me to reduce the size (because I could see so many cells were being upsized with x8, x16 ... very little x1 drive strengths, and lots of buffer insertion, or alternatively the backend person would need to grow the floorplan. In some cases, growing the floorplan wasn't an option. The issue is when the growth of the design has already happened, which drives the floorplan, which might not be good if it wasn't necessary to overconstrain to begin with (and maybe result in a smaller floorplan). With my experiences (and collegues including R&D) with RC, by nature of the way it has worked for the last while, it is tuned to give best results when the target is set realistically with no margining in manipulating the clock period to be smaller, even on the tougher designs. For the backend tools, I agree, I've heard the same thing (and makes sense), these tools typically don't optimized as much as synthesis tools do(for one thing, it can't start with the RTL source to make major structural decisions up front of course). If the design is really tight, this is where physical synthesis may help such as with RC Physical. If you haven't heard about it, you can find some info on this datasheet link: www.cadence.com/.../encounter_rtlcompiler.pdf

Kenneth, I have d ...

Anonymous — Mon, 13 Jul 2009 23:56:21 GMT

Kenneth,

I have done enough benchmarking on various complex designs using different synthesis tools such as Get2Chip now RC, DC/DC-Ultra, Ambit-PKS, DC-Topo, Physical Compiler. I agree with you that quality of netlist matters most to backend tool.

But I don't think you can hand-off netlist with 0 margin to backend tool. If it is timing critical design and you don't synthesize with margin it simply won't meet timing after layout, period!

I also think floor plan and die-area will be more if netlist going to P&R doesn't have margin.

Final point, as far as I know from most of the backend engineers, Encounter and other backend tools don't optimize design as much as DC and RC does.

Sanjay

How to Pick a Synthesis Tool - The Right One for You - Part 2

Logic Design — Tue, 07 Jul 2009 14:15:36 GMT

By Kenneth Chang, Core Comp AE, Team FED . In my previous blog , I had written about how "Synthesis

I am looking for a p ...

Anonymous — Mon, 06 Jul 2009 12:14:46 GMT

I am looking for a possibility to use VHDL files inside OrCAD. Can you help me?

Test comment on blog ...

Anonymous — Tue, 02 Jun 2009 19:37:01 GMT

Test comment on blog post.

Friday Fun: The Secrets of EDA Mmarketing - Logic Design - Cadence Community

Friday Fun: The Secrets of EDA Mmarketing - Logic Design - Cadence Community — Fri, 08 May 2009 13:47:31 GMT

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I think this one s t ...

Anonymous — Sat, 02 May 2009 18:45:44 GMT

I think this one s the best way, and i have personal experience of this.. I usually learn while talking to some one of my field!!!