Logic Design

When Will We Move From RTL to TLM? I Need to Know!

Bob Loblaw — Mon, 08 Mar 2010 18:00:00 GMT

My esteemed colleague, Steve Brown, recently wrote a well-thought piece trying to forecast what it will take to move the bulk of design from RTL abstraction to transaction-level modeling (TLM). He uses the gate-level to RTL migration as a reference point...(read more)

What Can We Learn From The iPad About Chip Design?

Bob Loblaw — Wed, 03 Feb 2010 03:16:00 GMT

You probably heard that Apple announced a touchscreen tablet computer last week. The announcement came with a lot of talk of it defining a new product category. That's somewhat laughable, since tablet computers have been around for a few years. BUT...(read more)

RTL-to-GDSII Does Not Need Re-tooling - It Needs Re-definition!

Bob Loblaw — Mon, 25 Jan 2010 17:00:00 GMT

I recently saw a blog post written by a competitor on a purportedly neutral EDA blog, that called for a re-tooling of the RTL-to-GDSII flow. The argument was that for designs 20M gates or larger, you needed to synthesize at the chip-level, and synthesize...(read more)

My Wish List For The New Decade

Bob Loblaw — Tue, 29 Dec 2009 14:00:00 GMT

Okay, it's the holiday season and end of the year, so I'll combine it all and make a wish list for the new year (as it relates to chip design). Heck, it's the end of the decade - so why not make a wish list for the new decade? A decade is...(read more)

Wrapping Up 2009 With Some Reflections

Kenneth Chang — Wed, 23 Dec 2009 14:00:00 GMT

As many of my customers mentioned and no surprise, 2009 was a tough year. Regardless though, designs continued to get pumped out the door by aggressive design teams, putting products in eager customer hands. I constantly get mesmerized by the number of...(read more)

Attention RTL Compiler Customers! RC 9.1.200 Is Here

Bob Loblaw — Tue, 15 Dec 2009 16:50:00 GMT

Cadence's synthesis R&D team has an early holiday gift for our RTL Compiler customers. The 9.1.200 release (or as our release management system affectionally calls it, "RC9.1-s203") is now available for download. This release is mainly...(read more)

Innovation != Invention

Bob Loblaw — Tue, 03 Nov 2009 14:00:00 GMT

There's a common misperception, especially in technology fields, that invention and innovation are interchangeable terms. Innovation is a new solution to a problem, a new way of doing things, something that creates new markets and categories. Yes...(read more)

How Much Power Are You Leaving On The Table?

Bob Loblaw — Fri, 23 Oct 2009 13:00:00 GMT

Everybody is looking to reduce their chip's power consumption these days. Often a lot of reduction is needed in order to fit in the desired power envelope. Until now, designers of chips for wireless applications formed the majority of the power management...(read more)

Physically-Aware Synthesis: This Time it’s Different

Bob Loblaw — Fri, 16 Oct 2009 13:00:00 GMT

RTL Compiler Physical has been available for about 2 years now, and we're getting more customers all the time. But we still get the question - how is this different from physical synthesis tools like PKS or Physical Compiler? Those of you that were...(read more)

How-to Plans for ECOs - Advice From Experts

Team FED — Thu, 15 Oct 2009 13:00:00 GMT

By Bassilios Petrakis I often wonder whether designers plan out well in advance their ECO methodology and strategy for a project. For instance, how do they determine how many spare gates to add, what type, where to place them, how to connect them. Or...(read more)

SoC and remodeling cost estimation

Bob Loblaw — Tue, 06 Oct 2009 13:00:00 GMT

Over at Cadence's Industry Insights blog by Richard Goering , he has a great writeup of a panel at the Virtual SoC Conference entitled "Are SoC Development Costs Significantly Underrated?" In it, there was a great analogy comparing a chip...(read more)

Branching Out - My Twitter Experiment

Bob Loblaw — Mon, 05 Oct 2009 20:38:00 GMT

I enjoy writing on this blog, but I don't get to post nearly as much as I would like. So I am going to try posting more often over on Twitter. It should be less-formal and more conversational, which are both more up my alley. I will of course continue...(read more)

How Do Logic Designers Become Rock Stars?

Bob Loblaw — Tue, 22 Sep 2009 17:11:00 GMT

Cadence's new Chief Marketing Officer, John Bruggeman just published a guest post over at one of my oft-read blogs, EDA Graffiti . In it he talks about Intel's "rock stars" - our logic design brethren - and how the model of relying on...(read more)

The Current State of the Art for Physical Synthesis - A Response

jflieder — Mon, 14 Sep 2009 13:00:00 GMT

I am posting this detailed blog in response to an article posted on John's Semi-Blog regarding the current state of physical synthesis tools. I too have been involved in this domain all the way back to the Links to Layout methodology of the mid to...(read more)

Friday Fun: Tapeout!

Bob Loblaw — Fri, 11 Sep 2009 13:00:00 GMT

Well, this is the finale of this season of The Next Generation. In it, the Dante Semi team celebrates their on-time tapeout, thanks to adopting modern design methodologies. It also has a bit of intrigue at the end. Hopefully this series has been entertaining...(read more)