Logic Design

8 Users Compare RTL Compiler (RC) vs. Design Compiler (DC) on DeepChip.com

David Stratman — Mon, 20 Jun 2011 13:00:00 GMT

It was refreshing to see what happened when John Cooley made his latest request for reader feedback on his popular DeepChip website catering to the semiconductor design community. A request had come in from a previous DeepChip post prior to the Design...(read more)

Going 'Digital End-to-End' ... and Riding Your ECOs to the Finish Line

Kenneth Chang — Mon, 07 Feb 2011 18:00:00 GMT

Thinking of your next ASIC ECOs? It could be for today, or maybe you are considering your next ASIC ECO methodology. You are probably not alone ... most designs will go through ECOs , whether they are related to bug fixes (those 'oh oh' moments...(read more)

New Era Of SoC Design – Still Enabled By Logic Designers

Jack Erickson — Thu, 08 Jul 2010 13:00:00 GMT

If you were unable to attend Embedded/SoC Enablement Day at DAC, I encourage you to check out Richard Goering's writeup on the new era of SoC design being driven by applications . It describes how Gadi Singer of Intel discussed new TVs that are networked...(read more)

Now Available: Encounter RTL Compiler 10.1

Jack Erickson — Mon, 28 Jun 2010 18:50:00 GMT

The latest major release of Encounter ® RTL Compiler is available for download (look for "RC101"). Some of the highlights include: Quality of Silicon improvements. A lot of work continues to go into improving results, especially physical...(read more)

TSMC Reference Flow Adds TLM Support -- Here's Why

Jack Erickson — Fri, 11 Jun 2010 16:25:00 GMT

Every year as spring turns to summer, we can count on a new Reference Flow from TSMC. While the seasons are driven by the laws of nature, the Reference Flow is driven by the laws of Moore. Typically the new additions to the flow have to do with accounting...(read more)

EDA360: Enlightenment for Silicon Test

Ed JM — Fri, 21 May 2010 21:00:00 GMT

At a macro level EDA360 is about driving the semiconductor industry toward sustainable differentiation. It represents a Cadence mission to help its customers' customers achieve industry leadership and profitability through enabling technologies, methodologies...(read more)

Friday Fun: InCyte Chip Estimator infomercial

Jack Erickson — Fri, 14 May 2010 13:00:00 GMT

This is our second (and last, for now) foray into the genre of cheesy American commercial advertisement. Here was our first attempt . I've been fascinated with the infomercial approach ever since I received "The ShamWow" for Father's...(read more)

CDNLive! EMEA: Taking logic design beyond the imagination

Jack Erickson — Thu, 06 May 2010 15:07:00 GMT

With a tagline of "Go beyond your imagination", it was pretty clear that this year's CDNLive! EMEA event would not be a typical user conference. Of course it also kicked off just days after our EDA360 launch, so there was a lot of buzz around...(read more)

Enabling Profitable Silicon Production: A Learning ‘Neural’ Network for Yield Ramp

Ed JM — Fri, 30 Apr 2010 01:42:00 GMT

It can not be overstated that the continued health of the chip industry hinges on profitable nanometer production, which depends on yield ramp and yield gap closure. The widening yield gap -- the difference between actual and predicted yield -- and its...(read more)

What does EDA360 mean for logic designers?

Jack Erickson — Thu, 29 Apr 2010 04:23:00 GMT

If you've seen all the buzz this week about Cadence's EDA360 vision for a major shift in the EDA industry, you may be wondering as a logic designer - "where do I fit? Does Cadence still care about what I do?" The short answer is that...(read more)

The new ChipEstimate.com: The place to be for IP

Jack Erickson — Thu, 22 Apr 2010 05:53:00 GMT

If you are not yet familiar with the ChipEstimate.com site.....first, why not? It is the leading portal for design IP with over 200 IP suppliers and over 8,000 components available. The team behind the site has been hard at work making it an even more...(read more)

Logic Design and Test Design: Do they need each other?

Ed JM — Sat, 17 Apr 2010 07:30:00 GMT

Cadence has moved from traditional methods and product offerings for silicon test in favor of a new direction, which answers the title question. In 2008, Cadence recognized that while the Encounter Test product had outstanding quality of results, ease...(read more)

Friday Fun: Multi-objective optimization for your iteration problem

Jack Erickson — Fri, 16 Apr 2010 11:51:00 GMT

Here in the U.S., in recent years we've seen all kinds of commercials on TV for prescription pharmaceuticals. Needless to say, they have to figure out how to sell something that is very intangible in most cases. This is not unlike algorithm-oriented...(read more)

Why physical guides are like Kramer

Jack Erickson — Tue, 13 Apr 2010 00:20:00 GMT

There has been a lot of talk recently about improving synthesis predictability by passing forward "guides" to physical design. This was something that we investigated doing in RTL Compiler, too. That was 2003. So whenever I get asked by folks...(read more)

What Madonna Can Teach You About Chip Design

Jack Erickson — Fri, 26 Mar 2010 13:00:00 GMT

Rather than wandering too far off-track with this one, what celebrity is more well-known for successfully reinventing themselves than Madonna? And it's probably less about reinvention than it is about adapting to a changing marketplace. How many other...(read more)

When Will We Move From RTL to TLM? I Need to Know!

Jack Erickson — Mon, 08 Mar 2010 18:00:00 GMT

My esteemed colleague, Steve Brown, recently wrote a well-thought piece trying to forecast what it will take to move the bulk of design from RTL abstraction to transaction-level modeling (TLM). He uses the gate-level to RTL migration as a reference point...(read more)

What Can We Learn From The iPad About Chip Design?

Jack Erickson — Wed, 03 Feb 2010 03:16:00 GMT

You probably heard that Apple announced a touchscreen tablet computer last week. The announcement came with a lot of talk of it defining a new product category. That's somewhat laughable, since tablet computers have been around for a few years. BUT...(read more)

RTL-to-GDSII Does Not Need Re-tooling - It Needs Re-definition!

Jack Erickson — Mon, 25 Jan 2010 17:00:00 GMT

I recently saw a blog post written by a competitor on a purportedly neutral EDA blog, that called for a re-tooling of the RTL-to-GDSII flow. The argument was that for designs 20M gates or larger, you needed to synthesize at the chip-level, and synthesize...(read more)

My Wish List For The New Decade

Jack Erickson — Tue, 29 Dec 2009 14:00:00 GMT

Okay, it's the holiday season and end of the year, so I'll combine it all and make a wish list for the new year (as it relates to chip design). Heck, it's the end of the decade - so why not make a wish list for the new decade? A decade is...(read more)

Wrapping Up 2009 With Some Reflections

Kenneth Chang — Wed, 23 Dec 2009 14:00:00 GMT

As many of my customers mentioned and no surprise, 2009 was a tough year. Regardless though, designs continued to get pumped out the door by aggressive design teams, putting products in eager customer hands. I constantly get mesmerized by the number of...(read more)

Attention RTL Compiler Customers! RC 9.1.200 Is Here

Jack Erickson — Tue, 15 Dec 2009 16:50:00 GMT

Cadence's synthesis R&D team has an early holiday gift for our RTL Compiler customers. The 9.1.200 release (or as our release management system affectionally calls it, "RC9.1-s203") is now available for download. This release is mainly...(read more)

Innovation != Invention

Jack Erickson — Tue, 03 Nov 2009 14:00:00 GMT

There's a common misperception, especially in technology fields, that invention and innovation are interchangeable terms. Innovation is a new solution to a problem, a new way of doing things, something that creates new markets and categories. Yes...(read more)

How Much Power Are You Leaving On The Table?

Jack Erickson — Fri, 23 Oct 2009 13:00:00 GMT

Everybody is looking to reduce their chip's power consumption these days. Often a lot of reduction is needed in order to fit in the desired power envelope. Until now, designers of chips for wireless applications formed the majority of the power management...(read more)

Physically-Aware Synthesis: This Time it’s Different

Jack Erickson — Fri, 16 Oct 2009 13:00:00 GMT

RTL Compiler Physical has been available for about 2 years now, and we're getting more customers all the time. But we still get the question - how is this different from physical synthesis tools like PKS or Physical Compiler? Those of you that were...(read more)

How-to Plans for ECOs - Advice From Experts

Team FED — Thu, 15 Oct 2009 13:00:00 GMT

By Bassilios Petrakis I often wonder whether designers plan out well in advance their ECO methodology and strategy for a project. For instance, how do they determine how many spare gates to add, what type, where to place them, how to connect them. Or...(read more)

SoC and remodeling cost estimation

Jack Erickson — Tue, 06 Oct 2009 13:00:00 GMT

Over at Cadence's Industry Insights blog by Richard Goering , he has a great writeup of a panel at the Virtual SoC Conference entitled "Are SoC Development Costs Significantly Underrated?" In it, there was a great analogy comparing a chip...(read more)

Branching Out - My Twitter Experiment

Jack Erickson — Mon, 05 Oct 2009 20:38:00 GMT

I enjoy writing on this blog, but I don't get to post nearly as much as I would like. So I am going to try posting more often over on Twitter. It should be less-formal and more conversational, which are both more up my alley. I will of course continue...(read more)

How Do Logic Designers Become Rock Stars?

Jack Erickson — Tue, 22 Sep 2009 17:11:00 GMT

Cadence's new Chief Marketing Officer, John Bruggeman just published a guest post over at one of my oft-read blogs, EDA Graffiti . In it he talks about Intel's "rock stars" - our logic design brethren - and how the model of relying on...(read more)

The Current State of the Art for Physical Synthesis - A Response

jflieder — Mon, 14 Sep 2009 13:00:00 GMT

I am posting this detailed blog in response to an article posted on John's Semi-Blog regarding the current state of physical synthesis tools. I too have been involved in this domain all the way back to the Links to Layout methodology of the mid to...(read more)

Friday Fun: Tapeout!

Jack Erickson — Fri, 11 Sep 2009 13:00:00 GMT

Well, this is the finale of this season of The Next Generation. In it, the Dante Semi team celebrates their on-time tapeout, thanks to adopting modern design methodologies. It also has a bit of intrigue at the end. Hopefully this series has been entertaining...(read more)

RTL Power Estimation

Jack Erickson — Tue, 08 Sep 2009 16:00:00 GMT

RTL power estimation is a concept that has existed for a long time. The earlier that you can understand where power is consumed by your chip, the easier it is to make a positive impact. The challenge of course is obtaining accurate estimates. It is easy...(read more)

Friday Fun: A Last-minute ECO

Jack Erickson — Fri, 04 Sep 2009 13:00:00 GMT

In this week's episode, the Dante Semi team is about to tape out when they get a last minute spec adjustment from their primary customer. Does this sound familiar? How will they make the change and verify it quickly enough to be able to tape out on...(read more)

Friday Fun: Cutting Ties to the Past

Jack Erickson — Fri, 28 Aug 2009 13:00:00 GMT

In last week's installment , we left the Dante Semiconductor team when they were nearing tapeout, but their old vendor was asserting its own interests over that of the project. In this week's episode, the team comes together to break the final...(read more)

Friday Fun: Adopting New Low-power Design Techniques

Jack Erickson — Fri, 21 Aug 2009 13:00:00 GMT

This week's episode has the Dante Semi team employing some new low power design techniques, and using Conformal Low Power to verify their implementation of them. You will also see how the verification team uses low power simulation with Incisive to...(read more)

Friday Fun: Modern Methodology Has Benefits

Jack Erickson — Fri, 14 Aug 2009 12:00:00 GMT

In this week's episode of "The Next Generation", the Dante Semi team reviews the project status after adopting many new techniques, such as power shutoff, assertion-based verification, physical synthesis, and multi-supply multi-voltage optimization...(read more)

Automatically Identify, Fix, and Prevent Congestion With RTL Compiler Physical

Team FED — Tue, 11 Aug 2009 15:30:00 GMT

By Ankush Sood Principal Product Engineer Congestion is at the heart of the design closure challenge today. With smaller cell dimensions, increased chip-size and an inclination of design houses to reduce metal layers available for routing (to save costs...(read more)

I Need ASIC IP. Where Can I Find Information?

Kenneth Chang — Fri, 07 Aug 2009 13:05:00 GMT

By Kenneth Chang. The world's best IP ecosystem is ChipEstimate.com . That's what we're hearing every day from our customers. Second to none as a solution, ChipEstimate.com took DAC by storm, with its incredible line up of IP Talks! sessions...(read more)

Friday Fun: The Next Generation is Back!

Jack Erickson — Fri, 07 Aug 2009 13:00:00 GMT

After a bit of a hiatus due to some production issues, we're resuming the series of The Next Generation episodes. This week's episode starts with a review of the previous episode since it was so long ago, and deals with how companies have to make...(read more)

Do You Also Need to be a DFT, STA, Verification, Low-Power, and Library Expert? Not Anymore!

Team FED — Tue, 04 Aug 2009 13:00:00 GMT

By Jack Marshall Sr. Tech Leader, Solutions Our R&D team has just released a major new feature in RTL Compiler 9.1.100. It is called "Quality Analyzer". I call it "RC QA" for short - since that's how you invoke the feature...(read more)

RTL Compiler's New "Spatial Technology"

Team FED — Tue, 28 Jul 2009 17:50:00 GMT

By Jeff Flieder Sr. Solutions Manager Over the last few years, RTL Compiler has added a significant number of features targeted toward users that require more physical awareness in their synthesis flow. We first introduced the PLE (Physical Layout Estimation...(read more)

DesignWare and AmbitWare Demystified - Why and When to Avoid?

Team FED — Fri, 24 Jul 2009 13:23:00 GMT

By Diego Hammerschlag Sr. Technical Leader Team FED Most, if not all, synthesis tools today support the use of Synopsys DesignWare or a vendor specific brand of <vendor>Ware such as Ambit's AmbitWare, Cadence's ChipWare and others. I have...(read more)

RC Design Explorer: Find the Right Balance of Power and Performance

Team FED — Fri, 24 Jul 2009 13:00:00 GMT

By Paul Weil Sr. Product Engineer You might be aware that RTL Compiler has had the ability to synthesize top-down to multi-supply multi-voltages (MSMV) and optimize across them. Lowering voltage levels can be a great way to reduce switching power, but...(read more)

How to Pick a Synthesis Tool - The Right One for You - Part 2

Team FED — Tue, 07 Jul 2009 13:00:00 GMT

By Kenneth Chang, Core Comp AE, Team FED . In my previous blog , I had written about how "Synthesis matters." Snippet below. <snip> I had a boss that once said that all synthesis tools are same. This guy knew his stuff, been in the industry...(read more)

Now Available: RTL Compiler 9.1.100

Jack Erickson — Tue, 30 Jun 2009 13:00:00 GMT

I'm pleased to announce that our latest version of RTL Compiler - version 9.1.100 - is now available. This release is a significant upgrade for RC users, I would encourage all our customers to check it out as soon as you can. Some of the highlights...(read more)

Free Online Training: Conformal LEC

Team FED — Mon, 22 Jun 2009 13:30:00 GMT

By Kenneth Chang Core Comp AE Team FED . If you didn't know, Conformal's very own AE team put together some cool training materials for their customers based on large demand to help both new and intermediate users. It's free. And it's...(read more)

Of Rights & Wrongs: The Bottom-up vs. Top-down Methododology Debate

Team FED — Mon, 22 Jun 2009 13:15:00 GMT

By Diego Hammerschlag Sr. Technical Leader Team FED The top-down vs. bottom-up methodology decision is one that design engineers should not take lightly. It carries ramifications throughout the hole flow and can certainly make or break a project if not...(read more)

New White Paper: Routing Congestion De-Mystified

Jack Erickson — Tue, 16 Jun 2009 18:46:00 GMT

Even though routing congestion sounds like a physical design problem, it can cause chip projects to miss schedules, miss performance targets, or result in a larger die size. These are problems that are shared across the project, so if you want to control...(read more)

Low Power Guide from Industry Leaders

Team FED — Thu, 28 May 2009 13:00:00 GMT

By Kenneth Chang, Core Comp AE, Frontend Solutions. Low power concerns continue to drive companies' needs for optimized ASIC methodologies, which is why one of the Si2 key initiatives continues to be the standardization of Low Power Intent. Below...(read more)

Live From Munich CDNLive: The Happenings

Team FED — Tue, 26 May 2009 13:00:00 GMT

By Kenneth Chang, Core Comp AE, Frontend Solutions. So what happened at CDNLive in Germany this year? I always wondered as well, having attended and co-presented papers only at CDNLive San Jose and curious about our other regional events. Luckily, I had...(read more)

Why Your Project Should Not Follow the Fate of the Mars Orbiter - Part I

Team FED — Mon, 25 May 2009 13:00:00 GMT

By Diego Hammerschlag Sr. Technical Leader Team FED The “Orbiter” was a spacecraft on a mission to study the planet Mars. Unfortunately, Lockheed Martin and NASA had a mix up using Imperial units (pounds, miles, etc.) and Metric units (kilometers...(read more)