Register for Cadence's Front End Design User Summit -- December 6, 2012 in San Jose
By Kenneth Chang
on November 27, 2012
Cadence is hosting a Front End Design Summit on Thursday, December 6, 2012 9:30am – 5:00pm at Cadence San Jose headquarters, 2655 Seely Avenue, Building 10. Logic designers will hear from customers including Cisco, Chelsio, PMC, Spansion, and Via...
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Filed under: Logic Design, conformal, encounter, RTL compiler, cadence, Kenneth Chang, Encounter Test, front end, front-end summit, front-end design
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Tips for Fixing Timing Violations and Adopting Best Practices for Optimization with RTL Compiler
By Sumeet Aggarwal
on August 7, 2012
Best Practices for Optimization What should be my considerations while preparing data? Libraries, HDL, Constraints... A good result from a synthesis tool depends greatly on the input data. An old saying "garbage in garbage out" is also true...
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Filed under: Logic Design, Synthesis, RTL compiler, rc, Functional Verification, fixing timing violations, boundary optimizations, optimizations
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Boost Productivity With Synthesis, Test and Verification Flow Rapid Adoption Kits (RAKs)
By Sumeet Aggarwal
on July 24, 2012
A focus on customer enablement across all Cadence sub-organizations has led to a cross-functional effort to identify opportunities to bring our customers to proficiency with our products and flows. Hence, Rapid Adoption Kits -- RAKs -- for Synthesis,...
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Filed under: Logic synthesis, Test, Logic Design, Verification, Incisive, conformal, Synthesis, RTL compiler, ATPG, rapid adoption kits, Encounter Test, customer enablement, EDI, RAKs, LEC, Incisive Enterprise Simulator, Incisive Unified Simulation
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8 Users Compare RTL Compiler (RC) vs. Design Compiler (DC) on DeepChip.com
By David Stratman
on June 20, 2011
It was refreshing to see what happened when John Cooley made his latest request for reader feedback on his popular DeepChip website catering to the semiconductor design community. A request had come in from a previous DeepChip post prior to the Design...
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Filed under: Logic synthesis, Low power , Logic Design, CPF, power management, Common Power Format, Synthesis, RTL, encounter, RTL compiler, cadence, synopsys, rc, methodology, DAC, Digital, Digital End-to-End, design comipler, DC, DeepChip, Cooley
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Going 'Digital End-to-End' ... and Riding Your ECOs to the Finish Line
By Kenneth Chang
on February 7, 2011
Thinking of your next ASIC ECOs? It could be for today, or maybe you are considering your next ASIC ECO methodology. You are probably not alone ... most designs will go through ECOs , whether they are related to bug fixes (those 'oh oh' moments...
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Filed under: Logic Design, conformal, Conformal ECO, encounter, ECO, Digital End-to-End, ECO Designer, ECOs
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New Era Of SoC Design – Still Enabled By Logic Designers
By Jack Erickson
on July 8, 2010
If you were unable to attend Embedded/SoC Enablement Day at DAC, I encourage you to check out Richard Goering's writeup on the new era of SoC design being driven by applications . It describes how Gadi Singer of Intel discussed new TVs that are networked...
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Filed under: Synthesis, RTL compiler, C-to-Silicon, TLM, EDA360, Silicon Realization, SoC Realization
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Now Available: Encounter RTL Compiler 10.1
By Jack Erickson
on June 28, 2010
The latest major release of Encounter ® RTL Compiler is available for download (look for "RC101"). Some of the highlights include: Quality of Silicon improvements. A lot of work continues to go into improving results, especially physical...
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Filed under: Logic Design. Power Shut-Off, Synthesis, multi-vt, turnaround time, RTL Compiler 10.1
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TSMC Reference Flow Adds TLM Support -- Here's Why
By Jack Erickson
on June 11, 2010
Every year as spring turns to summer, we can count on a new Reference Flow from TSMC. While the seasons are driven by the laws of nature, the Reference Flow is driven by the laws of Moore. Typically the new additions to the flow have to do with accounting...
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Filed under: RTL compiler, C-to-Silicon, TLM, EDA360, Silicon Realization
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EDA360: Enlightenment for Silicon Test
By Edward Malloy
on May 21, 2010
At a macro level EDA360 is about driving the semiconductor industry toward sustainable differentiation. It represents a Cadence mission to help its customers' customers achieve industry leadership and profitability through enabling technologies, methodologies...
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Filed under: Test, Logic Design, EDA360, ATPG
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Friday Fun: InCyte Chip Estimator infomercial
By Jack Erickson
on May 14, 2010
This is our second (and last, for now) foray into the genre of cheesy American commercial advertisement. Here was our first attempt . I've been fascinated with the infomercial approach ever since I received "The ShamWow" for Father's...
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Filed under: incyte, chip planning, Logic Design. Power Shut-Off, chip estimate, friday fun
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