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Logic Design Blog

New Technical Resources for Encounter Test Users on http://support.cadence.com

Hello Encounter Test Users, In this blog, I would like to introduce a few knowledge artifacts that will provide an easy way for you to learn about and stay productive with this product, technology, and methodology. In addition, this will also help to...  Read More »
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RTL Compiler (RC) Timing Analyzer (RTA) Flow

The design and physical implementation engineers involved in early to late stage synthesis require a flow that helps them investigate timing using a structured and physically aware approach. Cadence Encounter® RTL Compiler (RC) Timing Analyzer was...  Read More »
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New Rapid Adoption Kit on Encounter RTL Compiler: RC-Physical Low Power Flow

Cadence's Digital Front-End Design Team first introduced the concept of a Rapid Adoption Kit (RAK) , self-guided and learn-by-doing training material, over two and a half years ago, helping its users across the globe deploy new products and flows...  Read More »
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RTL Compiler Beginner’s Guides Available on Cadence Online Support

With shrinking design nodes, a significant portion of the delays are contributed by the wires rather than the cells. Traditional synthesis tools use fan-out-based wire-load models to provide wire delay information, which has led to significant differences...  Read More »
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Discover Programmable MBIST and Boundary Scan Insertion and Verification Flows Through RAKs

Cadence Encounter® Test uses breakthrough timing-aware and power-aware technologies to enable customers to manufacture higher quality, power-efficient silicon faster and at lower cost. Encounter Diagnostics identifies critical yield-limiting issues...  Read More »
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Register for Cadence's Front End Design User Summit -- December 6, 2012 in San Jose

Cadence is hosting a Front End Design Summit on Thursday, December 6, 2012 9:30am – 5:00pm at Cadence San Jose headquarters, 2655 Seely Avenue, Building 10. Logic designers will hear from customers including Cisco, Chelsio, PMC, Spansion, and Via...  Read More »
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Tips for Fixing Timing Violations and Adopting Best Practices for Optimization with RTL Compiler

Best Practices for Optimization What should be my considerations while preparing data? Libraries, HDL, Constraints... A good result from a synthesis tool depends greatly on the input data. An old saying "garbage in garbage out" is also true...  Read More »
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Boost Productivity With Synthesis, Test and Verification Flow Rapid Adoption Kits (RAKs)

A focus on customer enablement across all Cadence sub-organizations has led to a cross-functional effort to identify opportunities to bring our customers to proficiency with our products and flows. Hence, Rapid Adoption Kits -- RAKs -- for Synthesis,...  Read More »
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