Logic Design

8 Users Compare RTL Compiler (RC) vs. Design Compiler (DC) on DeepChip.com

2011-06-20T13:00:00Z

It was refreshing to see what happened when John Cooley made his latest request for reader feedback on his popular DeepChip website catering to the semiconductor design community. A request had come in from a previous DeepChip post prior to the Design Automation Conference (DAC) as follows: Are there any unbiased comparisons between the area and power performance of Synopsys Design Compiler and Cadence Encounter RTL Compiler synthesis? Knowing that in general engineers don't like to take sides...(read more)

Going 'Digital End-to-End' ... and Riding Your ECOs to the Finish Line

2011-02-07T18:00:00Z

Thinking of your next ASIC ECOs? It could be for today, or maybe you are considering your next ASIC ECO methodology. You are probably not alone ... most designs will go through ECOs , whether they are related to bug fixes (those 'oh oh' moments of silence), or intended functional changes (which are not out of the ordinary -- maybe your marketing department has requested the design team to add a new feature to the ASIC because of competitive pressures). Thus, planning for ECOs is a necessity...(read more)

New Era Of SoC Design – Still Enabled By Logic Designers

2010-07-08T13:00:00Z

If you were unable to attend Embedded/SoC Enablement Day at DAC, I encourage you to check out Richard Goering's writeup on the new era of SoC design being driven by applications . It describes how Gadi Singer of Intel discussed new TVs that are networked and can run apps on them (which for me is much more exciting than 3D). And Gadi was followed by Cadence's John Bruggeman, who connected this to the EDA360 vision and described some of what is required to make this happen. What jumped out...(read more)

Now Available: Encounter RTL Compiler 10.1

2010-06-28T18:50:00Z

The latest major release of Encounter ® RTL Compiler is available for download (look for "RC101"). Some of the highlights include: Quality of Silicon improvements. A lot of work continues to go into improving results, especially physical results. We have seen some early-adopter partners gain some significant area, timing, and power savings (these tend to be design-dependent and constraint-dependent, of course). Multi-vt algorithm improvements. We have done a lot of work in the multi...(read more)

TSMC Reference Flow Adds TLM Support -- Here's Why

2010-06-11T16:25:00Z

Every year as spring turns to summer, we can count on a new Reference Flow from TSMC. While the seasons are driven by the laws of nature, the Reference Flow is driven by the laws of Moore. Typically the new additions to the flow have to do with accounting for new process effects such as signal integrity, yield, and leakage power. But this year's flow, which is focused on 28nm, added support for TLM design . Why would TSMC care about transaction level modeling? And how does that apply to 28nm...(read more)

EDA360: Enlightenment for Silicon Test

2010-05-21T21:00:00Z

At a macro level EDA360 is about driving the semiconductor industry toward sustainable differentiation. It represents a Cadence mission to help its customers' customers achieve industry leadership and profitability through enabling technologies, methodologies, and services. Ultimately it is a charter for driving a global community forward in a transforming economic environment. This new charter, significant as it is, relies on fundamental changes in organizational philosophy and activity -- moving...(read more)

Friday Fun: InCyte Chip Estimator infomercial

2010-05-14T13:00:00Z

This is our second (and last, for now) foray into the genre of cheesy American commercial advertisement. Here was our first attempt . I've been fascinated with the infomercial approach ever since I received "The ShamWow" for Father's Day from my proud son, who then asked for some red wine to pour on our carpet so I could try it out. Anyway, these infomercials always do a good job showing the product in action. Here at Cadence we have some great chip estimation and planning technology...(read more)

CDNLive! EMEA: Taking logic design beyond the imagination

2010-05-06T15:07:00Z

With a tagline of "Go beyond your imagination", it was pretty clear that this year's CDNLive! EMEA event would not be a typical user conference. Of course it also kicked off just days after our EDA360 launch, so there was a lot of buzz around that. Cadence's CMO, John Bruggeman, kicked off the conference by sketching out exactly what EDA360 means so we got to hear the vision live from the source. I think a lot of folks were pleasantly surprised by this bold vision, and also surprised...(read more)

Enabling Profitable Silicon Production: A Learning ‘Neural’ Network for Yield Ramp

2010-04-30T01:42:00Z

It can not be overstated that the continued health of the chip industry hinges on profitable nanometer production, which depends on yield ramp and yield gap closure. The widening yield gap -- the difference between actual and predicted yield -- and its impact on profitability has far-reaching implications. This fundamental challenge has never been more increasingly critical as we face expanding parametric process variations. Volume diagnostics, along with statistical analysis and underlying root...(read more)

What does EDA360 mean for logic designers?

2010-04-29T04:23:00Z

If you've seen all the buzz this week about Cadence's EDA360 vision for a major shift in the EDA industry, you may be wondering as a logic designer - "where do I fit? Does Cadence still care about what I do?" The short answer is that what we've traditionally referred to as "logic design" is in many ways the nexus of the hardware side of this vision. When you think about what you do as a logic designer, it involves a lot of the aspects outlined - creating IP, verifying...(read more)

The new ChipEstimate.com: The place to be for IP

2010-04-22T05:53:00Z

If you are not yet familiar with the ChipEstimate.com site.....first, why not? It is the leading portal for design IP with over 200 IP suppliers and over 8,000 components available. The team behind the site has been hard at work making it an even more compelling destination for all things IP. For instance, verification IP is finally getting its recognition as being as important as the design IP itself. Since verification is such a bottleneck in the design process, anything that makes this task more...(read more)

Logic Design and Test Design: Do they need each other?

2010-04-17T07:30:00Z

Cadence has moved from traditional methods and product offerings for silicon test in favor of a new direction, which answers the title question. In 2008, Cadence recognized that while the Encounter Test product had outstanding quality of results, ease-of-use was lacking. What was perhaps most important was the recognition of a rapidly shifting design-production paradigm driven mainly by silicon process phenomena. With quality and optimization of production cost remaining R&D's highest priority...(read more)

Friday Fun: Multi-objective optimization for your iteration problem

2010-04-16T11:51:00Z

Here in the U.S., in recent years we've seen all kinds of commercials on TV for prescription pharmaceuticals. Needless to say, they have to figure out how to sell something that is very intangible in most cases. This is not unlike algorithm-oriented EDA software! So we decided to have some fun and make a commercial that describes our multi-objective optimization in Encounter RTL Compiler with embedded Encounter DFT Architect. If you want more information on multi-objective global optimization...(read more)

Why physical guides are like Kramer

2010-04-13T00:20:00Z

There has been a lot of talk recently about improving synthesis predictability by passing forward "guides" to physical design. This was something that we investigated doing in RTL Compiler, too. That was 2003. So whenever I get asked by folks if we would consider a similar approach in RTL Compiler Physical, I can safely say that we already have and we found that they do not predict with enough accuracy on a consistent basis. Given all we've learned here at Cadence over the years, I...(read more)

What Madonna Can Teach You About Chip Design

2010-03-26T13:00:00Z

Rather than wandering too far off-track with this one, what celebrity is more well-known for successfully reinventing themselves than Madonna? And it's probably less about reinvention than it is about adapting to a changing marketplace. How many other 1980's pop stars can still sell out arenas today? We also have some great "reinvention" examples in our industry - IBM transformed from mainframes to PC's to software and services. Apple transformed from PC's to consumer electronics...(read more)

When Will We Move From RTL to TLM? I Need to Know!

2010-03-08T18:00:00Z

My esteemed colleague, Steve Brown, recently wrote a well-thought piece trying to forecast what it will take to move the bulk of design from RTL abstraction to transaction-level modeling (TLM). He uses the gate-level to RTL migration as a reference point so that we can learn from history. He lists a lot of factors that enabled the mainstream shift from gate-level to RTL, and sketches out a similar list of what would be required to move from RTL to TLM. It's a long list. Having worked in the logic...(read more)

What Can We Learn From The iPad About Chip Design?

2010-02-03T03:16:00Z

You probably heard that Apple announced a touchscreen tablet computer last week. The announcement came with a lot of talk of it defining a new product category. That's somewhat laughable, since tablet computers have been around for a few years. BUT - the previous tablet computers were all based on notebook architectures and processors. They have essentially been notebook PC's enhanced with touchscreens and swivel displays. For a platform to be useful as a tablet, it has to be much more graphics...(read more)

RTL-to-GDSII Does Not Need Re-tooling - It Needs Re-definition!

2010-01-25T17:00:00Z

I recently saw a blog post written by a competitor on a purportedly neutral EDA blog, that called for a re-tooling of the RTL-to-GDSII flow. The argument was that for designs 20M gates or larger, you needed to synthesize at the chip-level, and synthesize in conjunction with placement. It also goes on to describe the verification problem of chips this size. It is clear that synthesis needs to work in conjunction with placement. This is why we have over 50 customers now using our RTL Compiler Physical...(read more)

My Wish List For The New Decade

2009-12-29T14:00:00Z

Okay, it's the holiday season and end of the year, so I'll combine it all and make a wish list for the new year (as it relates to chip design). Heck, it's the end of the decade - so why not make a wish list for the new decade? A decade is a long time in our industry. This year, my 7-year-old asked Santa for a 4G phone (based on clever advertising by Sprint, which obfuscates the fact that their "4G" is just WiMax and they currently only offer modems, no phones yet). A decade...(read more)

Wrapping Up 2009 With Some Reflections

2009-12-23T14:00:00Z

As many of my customers mentioned and no surprise, 2009 was a tough year. Regardless though, designs continued to get pumped out the door by aggressive design teams, putting products in eager customer hands. I constantly get mesmerized by the number of people who are buying iPhones, including co-workers. Here are just a few highlights from the digitial perspective for 2009 (in no particular order): ECOs continue to be a priority. For all of 2009, Conformal ECO was being used almost everywhere. ECO...(read more)

Attention RTL Compiler Customers! RC 9.1.200 Is Here

2009-12-15T16:50:00Z

Cadence's synthesis R&D team has an early holiday gift for our RTL Compiler customers. The 9.1.200 release (or as our release management system affectionally calls it, "RC9.1-s203") is now available for download. This release is mainly focused on improvements to the core synthesis engine, including: Runtime speedup for large designs. We're seeing increasing synthesis partition sizes, with 1M instance synthesis runs becoming more commonplace. It makes sense given the increasing...(read more)

Innovation != Invention

2009-11-03T14:00:00Z

There's a common misperception, especially in technology fields, that invention and innovation are interchangeable terms. Innovation is a new solution to a problem, a new way of doing things, something that creates new markets and categories. Yes, an invention can enable innovation, but it is not a prerequisite. Take the iPod as an example. When it came out in 2001, there were already plenty of MP3 players available. Most were flash-based, when flash memory was still very expensive. The mainstream...(read more)

How Much Power Are You Leaving On The Table?

2009-10-23T13:00:00Z

Everybody is looking to reduce their chip's power consumption these days. Often a lot of reduction is needed in order to fit in the desired power envelope. Until now, designers of chips for wireless applications formed the majority of the power management community. These days, it is applicable to all kinds of chips, both wireless and wired. Shutting down functional blocks is a great technique to reduce power, there are many blocks that cannot be shut down long enough to deliver power savings...(read more)

Physically-Aware Synthesis: This Time it’s Different

2009-10-16T13:00:00Z

RTL Compiler Physical has been available for about 2 years now, and we're getting more customers all the time. But we still get the question - how is this different from physical synthesis tools like PKS or Physical Compiler? Those of you that were around 10 years ago when physical synthesis was launched, and in the years leading up to that, certainly remember the promise that these tools would eliminate iterations with physical design. Of course they would accomplish this by bringing physical...(read more)

How-to Plans for ECOs - Advice From Experts

2009-10-15T13:00:00Z

By Bassilios Petrakis I often wonder whether designers plan out well in advance their ECO methodology and strategy for a project. For instance, how do they determine how many spare gates to add, what type, where to place them, how to connect them. Or, what is the impact of RTL coding style, aggressive design optimization, and hierarchy ungrouping on ECO predictability We recently conducted a Webinar on this exact topic based on customer experience, and would like share these useful tips and recommendations...(read more)

SoC and remodeling cost estimation

2009-10-06T13:00:00Z

Over at Cadence's Industry Insights blog by Richard Goering , he has a great writeup of a panel at the Virtual SoC Conference entitled "Are SoC Development Costs Significantly Underrated?" In it, there was a great analogy comparing a chip design project to a home remodeling project. This is an analogy I see lots of potential for. But let's first focus on that cost estimation. The panel's focus was on development costs, so I won't spend any more time on that. But what about...(read more)

Branching Out - My Twitter Experiment

2009-10-05T20:38:00Z

I enjoy writing on this blog, but I don't get to post nearly as much as I would like. So I am going to try posting more often over on Twitter. It should be less-formal and more conversational, which are both more up my alley. I will of course continue to post here, too. If you are interested, you can click here to follow me on Twitter . But please - let's make this a two-way conversation! Jack Erickson...(read more)

How Do Logic Designers Become Rock Stars?

2009-09-22T17:11:00Z

Cadence's new Chief Marketing Officer, John Bruggeman just published a guest post over at one of my oft-read blogs, EDA Graffiti . In it he talks about Intel's "rock stars" - our logic design brethren - and how the model of relying on these rock stars to design your chips is no longer sufficient. Integration of IP is now just important as creation of that IP by those rock stars. This should not offend you rock stars, after all the amount of logic that can fit on a die is growing...(read more)

The Current State of the Art for Physical Synthesis - A Response

2009-09-14T13:00:00Z

I am posting this detailed blog in response to an article posted on John's Semi-Blog regarding the current state of physical synthesis tools. I too have been involved in this domain all the way back to the Links to Layout methodology of the mid to late 90’s and there is no question that there were serious shortcomings in that type of an approach. Simply back-annotating the capacitance and then trying to optimize based on that data had a very limited value, and arguably no value in deep...(read more)

Friday Fun: Tapeout!

2009-09-11T13:00:00Z

Well, this is the finale of this season of The Next Generation. In it, the Dante Semi team celebrates their on-time tapeout, thanks to adopting modern design methodologies. It also has a bit of intrigue at the end. Hopefully this series has been entertaining and educational. We figured we would try something different, so it would be good to hear in the comments what you all thought of it. Do you like the video entertainment format? Do you want to see a season 2? etc. Enjoy! Jack Erickson...(read more)

RTL Power Estimation

2009-09-08T16:00:00Z

RTL power estimation is a concept that has existed for a long time. The earlier that you can understand where power is consumed by your chip, the easier it is to make a positive impact. The challenge of course is obtaining accurate estimates. It is easy if you are estimating at the chip-level and most of the power is consumed by macros and I/O's, since those vary very little. On the other hand you would want to make this measurement before you start developing RTL, so you can decide whether or...(read more)

Friday Fun: A Last-minute ECO

2009-09-04T13:00:00Z

In this week's episode, the Dante Semi team is about to tape out when they get a last minute spec adjustment from their primary customer. Does this sound familiar? How will they make the change and verify it quickly enough to be able to tape out on time? (Hint: Conformal ECO ). Enjoy! If video fails to launch click here . Enjoy! Jack Erickson...(read more)

Friday Fun: Cutting Ties to the Past

2009-08-28T13:00:00Z

In last week's installment , we left the Dante Semiconductor team when they were nearing tapeout, but their old vendor was asserting its own interests over that of the project. In this week's episode, the team comes together to break the final link so that they can move forward with taping out their chip. Incidentally this turns out to be quite a teambuilding event. Enjoy! Jack Erickson...(read more)

Friday Fun: Adopting New Low-power Design Techniques

2009-08-21T13:00:00Z

This week's episode has the Dante Semi team employing some new low power design techniques, and using Conformal Low Power to verify their implementation of them. You will also see how the verification team uses low power simulation with Incisive to functionally verify the behavior. It's all going great until an unwelcome visitor from their past tries to rain on their parade... Enjoy! Jack Erickson...(read more)

Friday Fun: Modern Methodology Has Benefits

2009-08-14T12:00:00Z

In this week's episode of "The Next Generation", the Dante Semi team reviews the project status after adopting many new techniques, such as power shutoff, assertion-based verification, physical synthesis, and multi-supply multi-voltage optimization. It looks like things are going well! And with all the new customers adopting these modern techniques from Cadence, they had a need for a new AE... Enjoy! Jack Erickson...(read more)

Automatically Identify, Fix, and Prevent Congestion With RTL Compiler Physical

2009-08-11T15:30:00Z

By Ankush Sood Principal Product Engineer Congestion is at the heart of the design closure challenge today. With smaller cell dimensions, increased chip-size and an inclination of design houses to reduce metal layers available for routing (to save costs), designs are getting more congested. The normal approach to solve congestion has been to increase the die size which increases design cost. Hence it is desirable to have a comprehensive implementation flow in place which tackles congestion from RTL...(read more)

I Need ASIC IP. Where Can I Find Information?

2009-08-07T13:05:00Z

By Kenneth Chang. The world's best IP ecosystem is ChipEstimate.com . That's what we're hearing every day from our customers. Second to none as a solution, ChipEstimate.com took DAC by storm, with its incredible line up of IP Talks! sessions with guest speakers from all sorts of world famous companies who are part of this huge ecosystem which helps customers every day make smarter decisions earlier in the design flow. ARM, Cadence, Chartered, Denali, PLDA, Synopsys, TCI, TSMC, Uniquify...(read more)

Friday Fun: The Next Generation is Back!

2009-08-07T13:00:00Z

After a bit of a hiatus due to some production issues, we're resuming the series of The Next Generation episodes. This week's episode starts with a review of the previous episode since it was so long ago, and deals with how companies have to make difficult EDA tool decisions in today's competitive times. Enjoy! Jack Erickson...(read more)

Do You Also Need to be a DFT, STA, Verification, Low-Power, and Library Expert? Not Anymore!

2009-08-04T13:00:00Z

By Jack Marshall Sr. Tech Leader, Solutions Our R&D team has just released a major new feature in RTL Compiler 9.1.100. It is called "Quality Analyzer". I call it "RC QA" for short - since that's how you invoke the feature (rc -qa). It's our first attempt at producing an integrated, multi-checking, front end design, signoff, analysis, and debug tool. It works at the RTL block level, the RTL Chip Level and at the Gate level. RC QA utilizes, organizes and analyzes information...(read more)

RTL Compiler's New "Spatial Technology"

2009-07-28T17:50:00Z

By Jeff Flieder Sr. Solutions Manager Over the last few years, RTL Compiler has added a significant number of features targeted toward users that require more physical awareness in their synthesis flow. We first introduced the PLE (Physical Layout Estimation) flow that allows a very low impact way to accurately model 80-90% of the wires in a design in order to take the most advantage of RC's advance global optimization algorithms in a physical context. We then introduced RC-Physical (RCP), which...(read more)

DesignWare and AmbitWare Demystified - Why and When to Avoid?

2009-07-24T13:23:00Z

By Diego Hammerschlag Sr. Technical Leader Team FED Most, if not all, synthesis tools today support the use of Synopsys DesignWare or a vendor specific brand of <vendor>Ware such as Ambit's AmbitWare, Cadence's ChipWare and others. I have been frequently asked on the purpose of <vendor>Ware being that many of the functions implemented by DesignWare and its derivatives are readily supported by the tools today using much simpler higher level constructs. <vendor>Ware is used...(read more)

RC Design Explorer: Find the Right Balance of Power and Performance

2009-07-24T13:00:00Z

By Paul Weil Sr. Product Engineer You might be aware that RTL Compiler has had the ability to synthesize top-down to multi-supply multi-voltages (MSMV) and optimize across them. Lowering voltage levels can be a great way to reduce switching power, but it comes at the cost of reducing performance. As we have talked to customers, we have found that many do not take advantage of this opportunity to reduce power because they do not know how to find the right minimum voltage levels that still allow them...(read more)

How to Pick a Synthesis Tool - The Right One for You - Part 2

2009-07-07T13:00:00Z

By Kenneth Chang, Core Comp AE, Team FED . In my previous blog , I had written about how "Synthesis matters." Snippet below. <snip> I had a boss that once said that all synthesis tools are same. This guy knew his stuff, been in the industry forever. He said "synthesizing with Tool X may give different results from Tool Y, but once it gets into P&R, it was all the same, P&R will take care of the rest." In a heavy benchmark, I proved him wrong. Synthesis does matter...(read more)

Now Available: RTL Compiler 9.1.100

2009-06-30T13:00:00Z

I'm pleased to announce that our latest version of RTL Compiler - version 9.1.100 - is now available. This release is a significant upgrade for RC users, I would encourage all our customers to check it out as soon as you can. Some of the highlights include: Quality of Silicon improvements. For timing-critical designs, we have seen some pretty good improvements in terms of performance and area. Yes, this holds up in physical design as well. Capacity improvements. On average, this release shows...(read more)

Free Online Training: Conformal LEC

2009-06-22T13:30:00Z

By Kenneth Chang Core Comp AE Team FED . If you didn't know, Conformal's very own AE team put together some cool training materials for their customers based on large demand to help both new and intermediate users. It's free. And it's personal with Clay and Bruce. You may have even worked with them in the past! Click here to get free Conformal LEC Training and give it a try! (if you don't have a Sourcelink account, it's easy to apply. Sign-up here )...(read more)

Of Rights & Wrongs: The Bottom-up vs. Top-down Methododology Debate

2009-06-22T13:15:00Z

By Diego Hammerschlag Sr. Technical Leader Team FED The top-down vs. bottom-up methodology decision is one that design engineers should not take lightly. It carries ramifications throughout the hole flow and can certainly make or break a project if not careful. Such methodology decision can impact: Quality of Silicon (QoS) Equivalency Checking DFT implementation Reuse methodology ECO methodology Schedule These are only a few important parameters of the many that the top-down / bottom-up debate can...(read more)

New White Paper: Routing Congestion De-Mystified

2009-06-16T18:46:00Z

Even though routing congestion sounds like a physical design problem, it can cause chip projects to miss schedules, miss performance targets, or result in a larger die size. These are problems that are shared across the project, so if you want to control the success of your chip design project, it is something to be concerned about. But still, what can a logic designer do about it? Fortunately, today's physically-aware synthesis tools like RTL Compiler can help relieve many congestion issues...(read more)

Low Power Guide from Industry Leaders

2009-05-28T13:00:00Z

By Kenneth Chang, Core Comp AE, Frontend Solutions. Low power concerns continue to drive companies' needs for optimized ASIC methodologies, which is why one of the Si2 key initiatives continues to be the standardization of Low Power Intent. Below is just a couple of snapshots of posters which show the value that the Power Forward Initiative members, Si2's committee and its standards bring to the ASIC community, including a downloadable free Low Power Guide . Actually, it's more than just...(read more)

Live From Munich CDNLive: The Happenings

2009-05-26T13:00:00Z

By Kenneth Chang, Core Comp AE, Frontend Solutions. So what happened at CDNLive in Germany this year? I always wondered as well, having attended and co-presented papers only at CDNLive San Jose and curious about our other regional events. Luckily, I had the opportunity to co-author/present a paper this year in Munich so here's a glimpse on 'the happenings' from my view: (1) Attendance was good! Nothing majorly different from San Jose's event. Lots of people networking and learning...(read more)

Why Your Project Should Not Follow the Fate of the Mars Orbiter - Part I

2009-05-25T13:00:00Z

By Diego Hammerschlag Sr. Technical Leader Team FED The “Orbiter” was a spacecraft on a mission to study the planet Mars. Unfortunately, Lockheed Martin and NASA had a mix up using Imperial units (pounds, miles, etc.) and Metric units (kilometers, kilograms, etc.) Bad things happen to spacecraft when such mix ups occur. The Orbiter was no exception to this and after entering orbit at 57 km, instead of the 140 km it was supposed to, it quickly disintegrated due to the material stress induced...(read more)