Logic Design

When Will We Move From RTL to TLM? I Need to Know!

2010-03-08T18:00:00Z

My esteemed colleague, Steve Brown, recently wrote a well-thought piece trying to forecast what it will take to move the bulk of design from RTL abstraction to transaction-level modeling (TLM). He uses the gate-level to RTL migration as a reference point so that we can learn from history. He lists a lot of factors that enabled the mainstream shift from gate-level to RTL, and sketches out a similar list of what would be required to move from RTL to TLM. It's a long list. Having worked in the logic...(read more)

What Can We Learn From The iPad About Chip Design?

2010-02-03T03:16:00Z

You probably heard that Apple announced a touchscreen tablet computer last week. The announcement came with a lot of talk of it defining a new product category. That's somewhat laughable, since tablet computers have been around for a few years. BUT - the previous tablet computers were all based on notebook architectures and processors. They have essentially been notebook PC's enhanced with touchscreens and swivel displays. For a platform to be useful as a tablet, it has to be much more graphics...(read more)

RTL-to-GDSII Does Not Need Re-tooling - It Needs Re-definition!

2010-01-25T17:00:00Z

I recently saw a blog post written by a competitor on a purportedly neutral EDA blog, that called for a re-tooling of the RTL-to-GDSII flow. The argument was that for designs 20M gates or larger, you needed to synthesize at the chip-level, and synthesize in conjunction with placement. It also goes on to describe the verification problem of chips this size. It is clear that synthesis needs to work in conjunction with placement. This is why we have over 50 customers now using our RTL Compiler Physical...(read more)

My Wish List For The New Decade

2009-12-29T14:00:00Z

Okay, it's the holiday season and end of the year, so I'll combine it all and make a wish list for the new year (as it relates to chip design). Heck, it's the end of the decade - so why not make a wish list for the new decade? A decade is a long time in our industry. This year, my 7-year-old asked Santa for a 4G phone (based on clever advertising by Sprint, which obfuscates the fact that their "4G" is just WiMax and they currently only offer modems, no phones yet). A decade...(read more)

Wrapping Up 2009 With Some Reflections

2009-12-23T14:00:00Z

As many of my customers mentioned and no surprise, 2009 was a tough year. Regardless though, designs continued to get pumped out the door by aggressive design teams, putting products in eager customer hands. I constantly get mesmerized by the number of people who are buying iPhones, including co-workers. Here are just a few highlights from the digitial perspective for 2009 (in no particular order): ECOs continue to be a priority. For all of 2009, Conformal ECO was being used almost everywhere. ECO...(read more)

Attention RTL Compiler Customers! RC 9.1.200 Is Here

2009-12-15T16:50:00Z

Cadence's synthesis R&D team has an early holiday gift for our RTL Compiler customers. The 9.1.200 release (or as our release management system affectionally calls it, "RC9.1-s203") is now available for download. This release is mainly focused on improvements to the core synthesis engine, including: Runtime speedup for large designs. We're seeing increasing synthesis partition sizes, with 1M instance synthesis runs becoming more commonplace. It makes sense given the increasing...(read more)

Innovation != Invention

2009-11-03T14:00:00Z

There's a common misperception, especially in technology fields, that invention and innovation are interchangeable terms. Innovation is a new solution to a problem, a new way of doing things, something that creates new markets and categories. Yes, an invention can enable innovation, but it is not a prerequisite. Take the iPod as an example. When it came out in 2001, there were already plenty of MP3 players available. Most were flash-based, when flash memory was still very expensive. The mainstream...(read more)

How Much Power Are You Leaving On The Table?

2009-10-23T13:00:00Z

Everybody is looking to reduce their chip's power consumption these days. Often a lot of reduction is needed in order to fit in the desired power envelope. Until now, designers of chips for wireless applications formed the majority of the power management community. These days, it is applicable to all kinds of chips, both wireless and wired. Shutting down functional blocks is a great technique to reduce power, there are many blocks that cannot be shut down long enough to deliver power savings...(read more)

Physically-Aware Synthesis: This Time it’s Different

2009-10-16T13:00:00Z

RTL Compiler Physical has been available for about 2 years now, and we're getting more customers all the time. But we still get the question - how is this different from physical synthesis tools like PKS or Physical Compiler? Those of you that were around 10 years ago when physical synthesis was launched, and in the years leading up to that, certainly remember the promise that these tools would eliminate iterations with physical design. Of course they would accomplish this by bringing physical...(read more)

How-to Plans for ECOs - Advice From Experts

2009-10-15T13:00:00Z

By Bassilios Petrakis I often wonder whether designers plan out well in advance their ECO methodology and strategy for a project. For instance, how do they determine how many spare gates to add, what type, where to place them, how to connect them. Or, what is the impact of RTL coding style, aggressive design optimization, and hierarchy ungrouping on ECO predictability We recently conducted a Webinar on this exact topic based on customer experience, and would like share these useful tips and recommendations...(read more)

SoC and remodeling cost estimation

2009-10-06T13:00:00Z

Over at Cadence's Industry Insights blog by Richard Goering , he has a great writeup of a panel at the Virtual SoC Conference entitled "Are SoC Development Costs Significantly Underrated?" In it, there was a great analogy comparing a chip design project to a home remodeling project. This is an analogy I see lots of potential for. But let's first focus on that cost estimation. The panel's focus was on development costs, so I won't spend any more time on that. But what about...(read more)

Branching Out - My Twitter Experiment

2009-10-05T20:38:00Z

I enjoy writing on this blog, but I don't get to post nearly as much as I would like. So I am going to try posting more often over on Twitter. It should be less-formal and more conversational, which are both more up my alley. I will of course continue to post here, too. If you are interested, you can click here to follow me on Twitter . But please - let's make this a two-way conversation! Jack Erickson...(read more)

How Do Logic Designers Become Rock Stars?

2009-09-22T17:11:00Z

Cadence's new Chief Marketing Officer, John Bruggeman just published a guest post over at one of my oft-read blogs, EDA Graffiti . In it he talks about Intel's "rock stars" - our logic design brethren - and how the model of relying on these rock stars to design your chips is no longer sufficient. Integration of IP is now just important as creation of that IP by those rock stars. This should not offend you rock stars, after all the amount of logic that can fit on a die is growing...(read more)

The Current State of the Art for Physical Synthesis - A Response

2009-09-14T13:00:00Z

I am posting this detailed blog in response to an article posted on John's Semi-Blog regarding the current state of physical synthesis tools. I too have been involved in this domain all the way back to the Links to Layout methodology of the mid to late 90’s and there is no question that there were serious shortcomings in that type of an approach. Simply back-annotating the capacitance and then trying to optimize based on that data had a very limited value, and arguably no value in deep...(read more)

Friday Fun: Tapeout!

2009-09-11T13:00:00Z

Well, this is the finale of this season of The Next Generation. In it, the Dante Semi team celebrates their on-time tapeout, thanks to adopting modern design methodologies. It also has a bit of intrigue at the end. Hopefully this series has been entertaining and educational. We figured we would try something different, so it would be good to hear in the comments what you all thought of it. Do you like the video entertainment format? Do you want to see a season 2? etc. Enjoy! Jack Erickson...(read more)