Test using Encounter RTL Compiler global synthesis inserts a complete test
infrastructure to assure high testability while reducing the cost-of-test with
on-chip test data compression.
solution highlights of Cadence Encounter® Test can also be described as
manufacturing test offering for logic and embedded memory IP
Single-pass logic synthesis, test insertion and pattern generation that can be
physically and power domain aware
cost of defect detection with higher quality test patterns and accurate silicon
to all design sizes from small mixed-signal to very large SoCs
coverage analysis and augmentation
Support for MBIST and LBIST testing
has become a critical concern for ASIC designers. Design for Test (DFT)
techniques provide measures to comprehensively test the manufactured device for
quality and coverage. One of the main DFT techniques or Encounter® Test
solution components available today is Logic built-in self-test (LBIST). The
LBIST is inserted into a design to generate patterns for self-testing. LBIST
allows for field/system testing without the need for automated test equipment
(ATE) and at times it is used during wafer/burn-in testing. Cadence Encounter® RTL
Compiler provides an automated way to insert LBIST logic, while Cadence Encounter®
Test provides support to generate the patterns and observe the responses.
Now the question is how quickly to find the right learning vehicle that helps discover what one doesn't already
Adoption Kits (RAKs) from Cadence help engineers learn foundational aspects of
Cadence tools and design and verification methodologies using a "DIY"
approach. Application notes, tutorials and videos also help develop a deep understanding of the subject.
this need in mind, Cadence Encounter® Test and RTL Compiler product development
teams, in February 2014, developed a RAK that introduces
the concepts of LBIST used to test logic test
structures. The RAK covers the insertion of structured test logic into the
digital portion of multiple designs using RTL Compiler, running LBIST Signature
Generation and Automatic Test Pattern Generation (ATPG) using Encounter Test,
running simulation with ncsim (IES), and Conformal LEC Verification.
At the end of this RAK, you should be
how to insert LBIST into a design
how X-sources need to be controlled during LBIST execution
the differences between Direct Access and JTAG LBIST, and when it is best to
apply each method
the scripts and files written out of RTL Compiler to be used by Encounter Test
for LBIST Signature Simulation
able to insert test points into a design to augment coverage
You can download your copy by clicking a link below, and use your Cadence
credentials to log on to the Cadence support website.
Test and RTL Compiler: Logic Built-In-Self-Test (LBIST)
We are covering following
technologies through our RAKs at this moment:
Test and Verification flow
Digital Implementation (EDI) System and Sign-off Flow
Custom IC and Sign-off Flow
and IP level Functional Verification
level verification and validation with Palladium XP
Please keep visiting http://support.cadence.com/raks to download your
copy of RAK.