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RTL Compiler (RC) Timing Analyzer (RTA) Flow

Comments(0)Filed under: RC-Physical, RAKs, timing bin, timing analyzer, rta, rc compiler

The design and physical implementation engineers involved in early to late stage synthesis require a flow that helps them investigate timing using a structured and physically aware approach. Cadence Encounter® RTL Compiler (RC) Timing Analyzer was developed to address exactly this need. It can be used in conjunction with multiple physical GUIs allowing physically aware timing debug analysis of a design in RC through a global view of the overall timing challenge, and via user-configurable dynamic binning of timing path groups

A timing bin is a collection of timing paths selected by the user. Timing bins can be iteratively sub-divided. RC Timing Analyzer is an intuitive GUI/TUI method of timing investigation of a design from within the RC cockpit.



The development effort does not just stop here, however. The Cadence team believes that learning new technology should be as fast and efficient as possible. To this end, Anil Thaker, Principal Product Engineer, developed a self-learning Rapid Adoption Kit (RAK) on the RTL Compiler Timing Analyzer (RTA) Flow.

Anil firmly believes that this RAK will enable Encounter RTL Compiler users to learn how to create and query timing bins using RTL Compiler. Also, the users will be well versed in using the report timing and physical GUIs to observe paths contained in timing bins.

Ercan Cetin and Ankush Sood from the Cadence Product Engineering team helped review this RAK. They note that users can view multiple paths in the timing view and cross probe directly into the physical view.

So, hurry up and get your free copy from Cadence Online Support http://support.cadence.com.

 Rapid Adoption Kits


Application Note(s)

RAK Database

RTL Compiler: RC Timing Analyzer (RTA) Flow



Download (116 MB)

Note: To access above docs, click a link and use your Cadence credentials to log on to the Cadence Online Support http://support.cadence.com website.

Here is link for complete list of all RAKs for our Digital Frond-End Design Flows.

Synthesis, Test and Verification flow

We keep them up-do-date based on your feedback and our continuous internal review cycle. We are also covering the following technologies through our RAKs at this moment:

Encounter Digital Implementation (EDI) System and Sign-off Flow
Virtuoso Custom IC and Sign-off Flow
Silicon-Package-Board Design
Verification IP
SOC and IP level Functional Verification
System level verification and validation with Palladium XP

Please visit http://support.cadence.com/raks to download any RAKs of interest.

We will continue to provide self-help content on Cadence Online Support, your 24/7 partner for learning more about Cadence tools, technologies, and methodologies as well as getting help in resolving issues related to Cadence software. If you are signed up for e-mail notifications, you will be notified of new solutions, application notes (technical papers), videos, manuals, etc.

Happy Learning!

Sumeet Aggarwal


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