We are often asked, by engineers doing
synthesis, "Does Encounter® RTL Compiler support ILM(s) - Interface
Logic Model(s) during synthesis? How to use ILM? What are its
In this blog, I will not only provide
some basic information about ILMs, but also point readers to a learn-by-doing content
on RC Hierarchical ILM flow packaged in a RAK (Rapid Adoption Kit).
Interface Logic Model (ILM) is a technique to model blocks in hierarchal
VLSI implementation flows. The advantage of the abstracted ILM approach is that
entire path (clock to clock path) is visible at top level for interface nets
unlike traditional block based hierarchal implementation flow. That gives
better accuracy in analysis for interface nets at negligible additional memory
and runtime overhead.
There is no specific requirement for ILM models. You would
generate an ILM model for your implemented block, in Encounter® Digital Implementation
or Encounter® RTL Compiler. The requirement will change at top level in terms
of constraints. You will need to read your top-level constraints which include
references to block as well. So you will need full top-level constraints so
that exceptions like false-paths between top and block etc. are correctly
Here is the simple version of using ILM at top level:
read_ilm -basename <path of ILM of other blocks> -module
assemble_design # This will load data for ILMs
<TOP level constraints and setup>
Write_design -hierarchical -encounter
Also, in today's high utilization designs, following steps are
- Possibility of extra logic optimization at top
- Consequent possibility of creating
placement/routing resources at SoC level
- Hence, TOP level
- However, massive design sizes can push
software to its limit
hierarchical synthesis required
Benefits of ILM:
highly accurate representations of the original design. ILMs do not abstract. They
simply discard what is not required for modeling boundary timing.
have very small memory footprint leading to very fast runtimes.
in the timing characteristics of an ILM, when compared to the original netlist,
are easy to debug because the interface logic is maintained.
generation runtime using ILMs is fast because identifying the interface logic
for a design is a structural operation that is performed by analyzing circuit
for a mapped design, can be created at any stage during design flow - postSynth,
prePlace, preCts, postCts or postRoute.
provide an accurate and robust model generation solution for chip-level
analysis in a hierarchical design flow.
In general, Interface logic
contains all the circuitry leading from I/O ports to edge-triggered registers
called interface registers. The clock tree leading to interface registers is
maintained as it is in ILM. Logic/circuitry that only consists of
register-to-register paths on a block is not a part of an ILM.
The SI ILM logic model, also
known as XILM, contains logic and capacitance information to model SI effects
on interface timing.
Keeping this in mind, Shreyash
Shukla, Principal PE, Synthesis R&D, Cadence Design Systems has
developed a new RAK on RTL Compiler:
Hierarchical ILM (Interface Logic Model) Flow, that
will help user walk through the complete Hierarchical ILM flow available in RC,
including generating ILM from RC and assemble design flow for ILM blocks.
RTL Compiler: Hierarchical ILM (Interface Logic Model) Flow
10 Dec, 2013
We are covering the following
technologies through our RAKs at this moment:
Synthesis, Test and Verification flow
Encounter Digital Implementation (EDI) System and Sign-off Flow
Virtuoso Custom IC and Sign-off Flow
SOC and IP level Functional Verification
System level verification and validation with Palladium XP
Please visit http://support.cadence.com/raks
to download any RAKs of interest.
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