Cadence Encounter® Test uses breakthrough timing-aware and power-aware technologies to enable customers to manufacture higher quality, power-efficient silicon faster and at lower cost. Encounter Diagnostics identifies critical yield-limiting issues and locates their root causes to speed yield ramp. Encounter Test is integrated with Encounter RTL Compiler global synthesis and inserts a complete test infrastructure to assure high testability while reducing the cost-of-test with on-chip test data compression.
Very recently, the Cadence Encounter Test and Diagnostic and RTL Compiler Product Development teams developed two beginner-to-advanced level Rapid Adoption Kits on Programmable Memory BIST and Boundary Scan Insertion and Verification, which can improve your productivity and maximize the benefits of Cadence tools and technologies.
In the past few blog posts, I have written so much about Rapid Adoption Kits - RAKs, which teams within Cadence uniquely developed in 2011, that you probably won't need other details other than just knowing that a RAK is a package of different knowledge pieces (presentations and application notes along with a demo design database with relevant scripts and instructions) that can be downloaded to "play around" a particular feature or capability of the tool without active support.
Memory built-in self-test (MBIST) logic is inserted, using the "insert_dft mbist" command, into a design within an RTL Compiler session. It is a proven, simple, and straight-forward flow for hundreds of designs, mostly targeted towards >65nm technologies. However, Cadence Encounter Test R&D described that there was a need for a programmable unified engine that provides greater flexibility for area reduction and can target all technology nodes with extensibility into the future.
I know you will now be interested to get answers, in detail, for the following questions:
- How and why is Programmable MBIST used to test embedded memories?
- How to insert Programmable MBIST?
- What are the scripts and files written out of RTL Compiler to be used by Encounter Test for pattern generation and verification?
- How are the checks performed by application to verify the correctness of memory test related information?
And here is Cadence Encounter Test R&D, helping you discover the same through its latest powerful RAK on Encounter Test and RTL Compiler: Programmable Memory Built-In-Self-Test (PMBIST)
Rapid Adoption Kits
Encounter Test and RTL Compiler: Programmable Memory Built-In-Self-Test (PMBIST)
Download (6 MB)
This RAK Includes RTL Compiler (RC) and Encounter Test (ET) Rapid Adoption Kit with demo design. It demonstrates the insertion and validation of the Programmable MBIST solution. This kit contains three main areas: PMBIST insertion within a standard RC-DFT flow, construction and validation of Memory Views (a representation of the memory structure within the design), and development of a test plan with algorithms for testing the memory. These steps are accomplished with a validation process using Incisive Simulator (NCSim).
Boundary Scan typically used in board-level testing. I am pretty sure users at this community forum or users of Cadence Encounter Test and RTL Compiler tools want to understand how and why Boundary Scan is used to isolate the different chips on a board for testing, how to insert Boundary Scan into a chip, what are the scripts and files written out of RTL Compiler to be used by Encounter Test for Boundary Scan Verification, and which are the checks performed by Encounter Test to verify the correctness and standard compliance of Boundary Scan.
This second new RAK on Encounter Test and RTL Compiler: IEEE 1149.1 and 1149.6 Boundary Scan covers all the answers and introduces how to insert Boundary Scan using RTL Compiler, perform Boundary Scan Verification using Encounter Test, and simulate the generated test patterns in Incisive Simulator (NCSim).
Rapid Adoption Kits
Encounter Test and RTL Compiler: IEEE 1149.1 and 1149.6 Boundary Scan
Download (6 MB)
This RAK kit includes RTL Compiler (RC) and Encounter Test (ET) Rapid Adoption Kit with demo design. It demonstrates the insertion and verification of IEEE 1149.1 Boundary Scan, with and without pre-instantiated Scan Segments, Embedded I/O multi-PAD cells, user-defined JTAG macro, and custom TDRs. This kit also demonstrates IEEE 1149.6 Boundary Scan with differential and AC-coupled I/Os. The user is walked through the steps for insertion of Boundary Scan in RC and then through the steps for verification of the inserted structures in ET.
Through our RAKs, we currently cover:
Synthesis, Test and Verification Flow
Encounter Digital Implementation (EDI) System and Sign-off Flow
Virtuoso Custom IC and Sign-off Flow
SOC and IP Level Functional Verification
System Level Verification and Validation with Palladium XP
Please keep visiting http://support.cadence.com/raks to download your copy of our RAKs.
We will continue to provide self-help content on Cadence Online Support, your 24/7 partner for getting help in resolving issues related to Cadence software or in learning Cadence tools and technologies. If you are signed up for e-mail notifications, you'll notice new solutions, application notes (technical papers), videos, manuals, etc.
Note: To access above docs, click a link and use your Cadence credentials to logon to the Cadence Online Support http://support.cadence.com website.