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TSMC Reference Flow Adds TLM Support -- Here's Why

Comments(0)Filed under: RTL compiler, C-to-Silicon, TLM, EDA360, Silicon Realization

Every year as spring turns to summer, we can count on a new Reference Flow from TSMC. While the seasons are driven by the laws of nature, the Reference Flow is driven by the laws of Moore. Typically the new additions to the flow have to do with accounting for new process effects such as signal integrity, yield, and leakage power. But this year's flow, which is focused on 28nm, added support for TLM design. Why would TSMC care about transaction level modeling? And how does that apply to 28nm?

The short answer is Silicon Realization. It's no secret that TSMC would like to get designs into successful volume silicon as quickly as possible. And as with each new process node, the designs that will be done at 28nm will be larger, more complex, and higher volume than anything before. In order to address these challenges, it has become imperative to design at a higher-level of abstraction. Plus with today's chips being much more software-driven, it's becoming pretty clear that SystemC-based TLM design will be the most efficient start to the Silicon Realization process.

Of course, the same could be said for the past couple of process nodes, so why TLM now? Perhaps it is due to high-level synthesis finally maturing with tools like Cadence's C-to-Silicon Compiler, which connects TLM design to mainstream implementation by embedding RTL Compiler in order to perform accurate tradeoffs using the standard TSMC synthesis libraries. This unburdens logic designers from having to manually design and functionally verify micro-architectures - they can now concentrate on designing and verifying concepts, then using automated methods to realize them in silicon.

This is why TSMC cares, and it's a big win for logic designers.

Jack Erickson

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