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Enabling Profitable Silicon Production: A Learning ‘Neural’ Network for Yield Ramp

Comments(4)Filed under: Test, Logic Design, test escapes, defect testing, defect detection, DFT, diagnostics, DFM, low power test, yield, power test, test mode, Prediction, TMSC, QoS, Ed Malloy, root cause, yield gap, semiconductor, volume diagnostics, SDD, yield optimization, yield diagnostics, PDA, physical defect analysis, precision diagnostics, nanometerIt can not be overstated that the continued health of the chip industry hinges on profitable nanometer production, which depends on yield ramp and yield gap closure.  The widening yield gap -- the difference between actual and predicted yield -- and its impact on profitability has far-reaching implications.  This fundamental challenge has never been more increasingly critical as we face expanding parametric process variations.    Volume diagnostics, along with statistical analysis and underlying root-cause accuracy, provide a proven, productive, and predictable path to profitability. This is indeed a feedback path of monumental value.   Why? There are several reasons – both technical and economic.  While profitable yield is by no means a new concern, the need for a consistently effective solution moving forward has never been more urgent.  Several years ago IBS published the results of a study that showed yield ramps are slowing and design-process defects are growing.  At each new process node, the time needed to reach nominal yields doubled – not by days, or weeks, but months.  

The “Holy Grail” to Profitable Yield

 At the epicenter of nanometer yield challenge are increasing defects due to systemic design-process interactions. There are areas in which design features and process limitations are so close to the edge that they cross the line, resulting in subtle defects – typically categorized as timing, transition, or small delay defects (SDD).    Process technology advances, including changes in materials and aspect ratios of wires and vias, have introduced an increasing number of resistive bridges and vias, resulting in resistive shorts and opens.  And more aggressive reticle enhancement techniques introduce more physical complexity and more inaccuracy in modeling.  Traditional “in-line” yield diagnostic methodologies based on physical diagnostic analysis (PDA), including optical scanning and defect classification, do not adequately account for broader scale design-process interactions.  While process control and in-line inspection techniques can minimize process variability, these techniques have no knowledge of design, and therefore they cannot productively or predictively identify design-process defects.  And this predictability is the “Holy Grail” to profitable yield.   

Economic Influences and Implications of a Continuing Yield Gap    

In addition to the technological challenges, there are macro-economic influences -- a consumer driven industry with decreasing product windows, increasing volumes, and relentless price pressures which require foundries and IDMs to optimize yield in a much narrower time frame.  With macro-economic influences as they are, IC products do not reach expected yields during product lifetimes. This is unsustainable! Foundries are trying to copye by expanding the number and type of design rules. However, these too add to the overall complexity.    Simply put, physical analysis (i.e. precision failure analysis) and verification are not keeping pace with the increasing number of design-process interactions resulting in systemic yield loss. 

Modeling Accuracy in Diagnostics and Tighter DFM Links is the Key

So how do we resolve this?  As indicated earlier, the answer has been with us for some time, but fundamentals remain absent from some of today’s attempts at implementation. 

Volume diagnostics and statistical analysis are a proven, more intelligent and comprehensive method for identifying the root cause of design-process defects.  This methodology is also more effective at expediting the improvement of modeling and design rules to ensure profitable yield.  Along with a more comprehensive methodology, the necessary underlying accuracy in defect modeling, indentification, and classification enable an essential feedback path in the neural network, or learning system.  This system should necessarily include a broad range of fault models, algorithms and heuristics to isolate faults. And to ensure a closed loop learning network, we need increasingly tighter links to Design-for-Manufacturing (DFM) for improved design rule, modeling, and ATPG advancements. With greater accuracy in diagnostics, we can achieve productivity and predictability in physical analysis and physical design … and more meaningful strides will be made toward closing the yield gap and returning to more profitable production. 

Ed Malloy

Product Management

Encounter Test 



By Tom Valind on May 3, 2010
You state "Traditional “in-line” yield diagnostic methodologies  ... do not adequately account for ..."
I would argue that equally important is enhancing the "traditional"  delay test capabilities.  Using SDQL  (statistical/Small Delay Quality Level) analysis to drive a timing intelligent ATPG tool  ensures you are targetting the most prevalent small delay defects that are not "timing redundant" (so small they would not result in circuit failure)  or so large that a generic, no timing information, delay test will detect.  
Under "Modeling Accuracy"  I would add that knowledge of the physical layout can be an extremely valuable input to effectively using an ATPG tools "broad range of fault models, ...".  That physical knowledge could be applied to all instances of a specific library cell in the form of specific patterns to be applied or via lef/def physical layout information that identifies two nets that are physically close and are thus more likely to have a bridging defect.

By Ed JM on May 3, 2010
Tom, thank you for your thoughtful comments.  

Given the increasing parameters and associated variability these points you raise are  necessary for implementing a "smart" yield learning system - one that leads to greater accuracy and predictability between GDS and actual silicon.  

Our concern with design closure of key quality parameters (area, timing, power, testability) naturally extends to the actual silicon behavior through modeling accuracy.  Reducing iterations in both physical design and silicon production (respins) is critical to timely, profitable production.  

The awareness and conern iwth these issues must be shared with an equal sense of importance (and urgency) across logic, test, physical, and modeling design teams.    

By Tom Bartenstein on May 5, 2010
Ed... Wow... that's certainly a lot to parse through!
The primary comment I would make is that from my point of view, it's not a question of traditional inline methods vs. volume diagnostics.  In-line methods are improving and continue to prove enormously useful.  For instance, inspection tools can use the physical design to determine critical areas that require more attention, and therefore address some of the design/process interactions.  
From my point of view, the "Holy Grail" is to utilize inline methods along with methods such as volume diagnostics to complement each other in contributing to an overall understanding of processes, products, and the interactions between them.  Part of this vision includes feedback of the results of this understanding to both design and process "monitors" that span the spectrum from DFM rules to in-line inspection recipes.

By Ed JM on May 6, 2010
Thanks so much for sharing your comments ... and knowledge.  
Understood  - combined RnD investment/focus of in-line and volume diagnostics methods and efficiencies in feedback of resulting discoveries in design and process status (intelligence) will optimize the yield (and profitability) gap.  

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