If you've seen all the buzz this week about Cadence's EDA360
vision for a major shift in the EDA industry, you may be wondering as a logic
designer - "where do I fit? Does Cadence still care about what I do?"
The short answer is that what we've traditionally referred
to as "logic design" is in many ways the nexus of the hardware side of this
vision. When you think about what you do as a logic designer, it involves a lot
of the aspects outlined - creating IP, verifying it, integrating IP into the
SoC, and optimizing the integrated IP.
This "new world" is not something that Cadence made up, we've
observed this shift in the industry and we're adapting our focus to it. For
instance much of SoC design today consists of IP re-use, and that IP can come
from internal or external sources. Many larger semiconductor companies have IP
creation teams, and product teams that are responsible for integrating,
optimizing, and implementing the IP into a System-on-Chip. These product teams
often work closely with the software groups. Smaller companies of course combine
a lot of these functions but are essentially product-focused. They likely do
some IP creation but cannot make it to market re-inventing everything
So as a logic designer, what is your specialty? Here are the
major areas we see as opportunities to improve your company's profitability:
Create. Whenever or wherever hardware or software IP is
developed-be it for external or internal use-it must be created with
integration in mind. It must come with the right documentation, be fully
verified, and be configurable for the end application.
Integrate. Design teams must be able to rapidly integrate IP into
platforms, and then verify the complete SoC or platform, including interfaces
between analog and digital blocks as well as hardware and software.
Design teams must be able to reduce die and package costs while ensuring
quality, lowering power consumption, and trimming test costs through
automation. They must reduce the number of late-stage iterations.
Logic designers today span all three of these areas! However
you can probably see some differences between this vision and what you do
day-to-day. For instance IP creation is likely going to have to move to TLM in
order to be more portable and more easily integrated. The integration step will
require a higher-level focus that includes not only digital hardware IP, but
also analog and bare-metal software. And the optimization step requires more
than just meeting your timing targets - optimizing for area, power, and
testability, with physical awareness is absolutely necessary in order to ensure
that the SoC meets your profitability targets.
So yes, it will be different. It's already changing. However
as a logic designer you are in a great position to add value in this new model.
Cadence looks forward to helping you do that.
What do you think EDA360 means for logic designers?