Home > Community > Blogs > Logic Design > Attention RTL Compiler Customers! RC 9.1.200 Is Here
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Logic Design blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Attention RTL Compiler Customers! RC 9.1.200 Is Here

Comments(0)Filed under: Logic Design, QoS, leakage power, synthesis methodology logic design conformal lec aborts, multi-vt, RTL Compiler 9.1, OPCG, clock gating, runtime

Cadence's synthesis R&D team has an early holiday gift for our RTL Compiler customers. The 9.1.200 release (or as our release management system affectionally calls it, "RC9.1-s203") is now available for download.

This release is mainly focused on improvements to the core synthesis engine, including:

  • Runtime speedup for large designs. We're seeing increasing synthesis partition sizes, with 1M instance synthesis runs becoming more commonplace. It makes sense given the increasing size of chips....nobody wants to have to manage constraints for thousands of synthesis blocks. So we have worked directly with many customers to tune RC's runtimes for these large blocks, and we're seeing some great runtime improvements, ranging from 10% to over 70% faster.
  • Improved multi-vt optimization. Leakage power of course is a growing concern with each new process generation, and it is made worse when a design is timing-critical. The R&D team did a lot of work to the core structuring and mapping for multi-vt libraries so that RC can arrive at a more optimal tradeoff for your design goals.
  • Multi-objective clock gating. Basically we have made the clock gating algorithms more intelligent, so that they can better examine the entire solution space. What we've seen as a result is increased numbers of flops that get gated, but needing less clock gating logic in order to accomplish it. This is a win-win - less power, and less area!
  • More physically-aware incremental optimizations. First, clock gating is now physically-aware. So enable logic is assigned to physically-local flops. And some recently-added optimizations, such as sequential duplication and multi-bit cell inferencing, really should only be performed in a physical context. So this is exactly what we have done.
  • Integrated On-Product Clock Generation (OPCG). Working in conjunction with the Encounter Test engines, RC can now insert OPCG macros automatically. This is useful for high-speed designs that require test frequencies higher than can be supplied from the tester.

So all in all, there is a lot to look forward to this holiday season if you are an RTL Compiler customer. Enjoy!

Jack Erickson


Leave a Comment

E-mail (will not be published)
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.