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RTL Power Estimation

Comments(0)Filed under: Logic Design, low power design, RTL compiler, Jack Erickson, RTL power estimation

RTL power estimation is a concept that has existed for a long time. The earlier that you can understand where power is consumed by your chip, the easier it is to make a positive impact. The challenge of course is obtaining accurate estimates.  It is easy if you are estimating at the chip-level and most of the power is consumed by macros and I/O's, since those vary very little.  On the other hand you would want to make this measurement before you start developing RTL, so you can decide whether or not you need to choose different macros, IP, or libraries.  A tool like Cadence's InCyte Chip Estimator is perfect for that.

But what about pure RTL estimation?  As geometries shrink, obtaining reasonably accurate estimates gets more difficult.  Power consumption varies more widely depending on cell sizing or choice of voltage thresholds.  And those variables depend entirely on the timing criticality of the logic, and in smaller geometries that is more dependent on wire delays.  Thus it is impossible to estimate power consumption without understanding the design's timing and how the synthesis tool will structure the logic. 

This is why we built RTL power estimation right into RTL Compiler synthesis. Yes, it is built right-in, no extra license.  The thinking was that we are providing power feedback to aid in RTL development, much in the way synthesis provides timing and area feedback.  And you can annotate power consumption back to the RTL.  To get going, you'll first want to enable the RTL cross-probing with this attribute:

set_attribute hdl_track_filename_row_col true /

Then you need to build the RTL power models.  This of course uses your full SDC and utilizes the global synthesis engines so that the estimation is aware of how the logic will be structured and mapped for timing.  The command to build the RTL power models is:

build_rtl_power_models [-clean_up_netlist] [-clock_gating_logic] [-relative instances] [-design design


  • clean_up_netlist removes unreachable logic in the netlist as this can affect the accuracy of the estimation.
  • clock_gating_logic includes power estimation for the clock-gating logic. This will only have an effect if clock-gating insertion is enabled.
  • relative builds additional power models for the specified hierarchical instances. Use this option if you are interested in the relative power consumption of these hierarchical instances.

In most cases you would want to use those first two options.  The third option adds some runtime, but understanding relative power usage by hierarchy is often the most important metric at this stage.

Finally, to report power, the command is:

report power -rtl_cross_reference [-detail] [-flat ] [> file]


  • detail adds an abbreviated version of the RTL line and a list of the instances that correspond to that RTL line.
  • flat reports power information for all modules in the current hierarchy. If not specified, only power information for the top-level module in the current hierarchy is shown.
  • relative additionally builds models for the requested hierarchical instances. Use this option is you are interested in the relative power consumption of some blocks.

For those of you that use some form of RTL power estimation, Cadence or not, what are you using it for?  To feed back power usage to designers?  To regress power consumption at the chip level?  Leakage?  Switching?  Both?  etc. 


Comments encouraged!

Jack Erickson


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