Home > Community > Blogs > Logic Design > rc design explorer find the right balance of power and performance
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Logic Design blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

RC Design Explorer: Find the Right Balance of Power and Performance

Comments(0)Filed under: Logic synthesis, Low power , Logic Design, power, CPF, power management, MSV, performance, RTL Compiler 9.1, Paul WeilBy Paul Weil
Sr. Product Engineer


You might be aware that RTL Compiler has had the ability to synthesize top-down to multi-supply multi-voltages (MSMV) and optimize across them.  Lowering voltage levels can be a great way to reduce switching power, but it comes at the cost of reducing performance.  As we have talked to customers, we have found that many do not take advantage of this opportunity to reduce power because they do not know how to find the right minimum voltage levels that still allow them to meet their performance goals.

This is why we developed Design Explorer or "DEX" as we call it, in RTL Compiler 9.1.  The concept is simple - you just tell RC what range of voltage levels to explore for each domain, and RC will execute a bunch of exploration runs that generate a tabulated summary of the performance, power, and area for each exploration scenario.  These runs are what we call exploration runs  - the runtime is about 60% of a full synthesis run, but you get performance and power numbers within about 5% of what the full synthesis run would be.  This allows you to exhaustively explore your options and see which one(s) you would want to take through full synthesis.

If you consider a trivial example of a library with 3 possible voltage levels, and a design with 2 power domains, the possible MSMV architectures are 32=9.  That's a lot of scenarios to explore, and it's an extremely trivial example.  Even a more "typical" design that would have 4 power domains would result in 34=81 scenarios to explore.  There is just no way you would do this manually.  DEX enables this to be done automatically, and in parallel if you have the resources for it.

To get started, you would read all your normal design information - HDL, constraints, etc, including your library CPF - then specify the exploration domains.  In this example, our library has three voltages to explore - 0.8v, 0.9v, and 1.08v:

dex_define_exploration_power_domain -name default -default -voltage_range {0p8 1p08}

dex_define_exploration_power_domain -name macs -voltage_range {1p08 1p08} [find / -maxdepth 4 -inst ethernet_mac*]

dex_define_exploration_power_domain -name bridge_pcm -voltage_range {0p08 0p9} {bridge pcm_inst dma_mac_mult}

This defines the exploration domains - the first two will explore all three voltage levels, the third will only explore across 0.8v and 0.9v.  Then we need to create and execute the exploration scenarios:

dex_create_exploration_scenarios -design ${DESIGN}

dex_execute_exploration_scenarios -design ${DESIGN}

Once the runs are done, the summary report and detailed reports for each scenario will be available.  The summary report is generated by:

dex_report qor_summary -design ${DESIGN}

Specific scenario reports can be generated as-needed. For a specifc thread/scenario:

dex_report thread_info -design ${DESIGN} -thread thread_3

Once you have decided what scenario looks like it will give you the balance of performance, power, and area that you're looking for, you can run it through a full synthesis by writing out the scripts and CPF for that scenario (scenario #3 in this case):

dex_write_scenario -scenario scenario_3

From there you could do a full synthesis in RC or even with RC-Physical.

This was a quick overview - there is a full chapter on this capability in the Low Power in Encounter RTL Compiler user guide.  But hopefully it gives you an idea of how you can take advantage of this new capability to get started with an MSMV approach to greatly reduce power without compromising your performance or schedule.

Comments(0)

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.