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DesignWare and AmbitWare Demystified - Why and When to Avoid?

Comments(0)Filed under: Logic synthesis, Low power , Logic Design, logic low power design, Synthesis, QoS, synopsys, logic design, performance, innovation, FED, TeamFED, synthesis methodology, Diego Hammerschlag

By Diego Hammerschlag
Sr. Technical Leader
Team FED 

Most, if not all, synthesis tools today support the use of Synopsys DesignWare or a vendor specific brand of <vendor>Ware such as Ambit's AmbitWare, Cadence's ChipWare and others. I have been frequently asked on the purpose of <vendor>Ware being that many of the functions implemented by DesignWare and its derivatives are readily supported by the tools today using much simpler higher level constructs.

<vendor>Ware is used primarily in the following situations:

  1. To address shortcomings of legacy synthesis tools and/or specifications
  2. Reduce implementation time & risk for modules with limited or no value-add
  3. Purchased IP
  4. Legacy support

I will first cover (2), (3), and (4) while (1) will be covered later in more detail

(2) Reduce implementation time & risk for modules with limited or no value-add:

<vendor>Ware not only covers simple design that can be easily coded using higher level constructs, but it also includes slightly more complex designs such as Error Code Correction(ECC), Cyclic Redundancy Checker(CRC), as well as others. These types of designs are well defined and well understood and frequently provide little opportunity for companies to differentiate their product hence it is sometimes attractive for users to take advantage of the pre-implemented benefits of <vendor>Ware. Not only that, but one could argue, and EDA vendors certainly do, that the reuse of such designs by many customers results in less likelihood of bugs and issues with their implementation.

(3) Purchased IP

Several vendors also market larger IP as <vendor>Ware. This is slightly different than what (1) and (2) cover. It refers to larger designs as well as associated verification environments or additional verification IP. This kind of vendor<Ware> includes PCI cores, USB cores, and others. These kinds of <vendor>Ware can have a substantial cost associated with it.

(4) Legacy support

Frequently <vendor>Ware is used and supported as a result of legacy designs and usage in third party IP

(1) To address shortcomings of the tools and/or specifications

To understand the main purpose of <vendor>Ware we need to go back some time. Early synthesis technology did a poor job, or was simply not capable, of optimizing datapath components such as adders and multipliers. Moreover, standards like IEEE1364-1995(Verilog HDL) did not have comprehensive support of signed arithmetic at the time. As a result, coding certain operations may have been cumbersome and error-prone at times. EDA vendors came up with <vendor>Ware to address these shortcomings in their tools and the specifications of the time. <vendor>Ware essentially addressed the issue by hard-coding and parametrizing certain operations. The recent "designWare minpower" announcement by Synopsys is a good illustration of an application of the <vendor>Ware solution. In that case, <vendor>Ware addresses Design Compiler's power optimization shortcomings.  

When & Why to Avoid <vendor>Ware?

<vendor>Ware was an adequate solution at the time but it has several drawbacks.

Restricts portability:  
EDA vendors would love you to use their brand of <vendor>Ware (DesignWare, AmbitWare, etc.) since to a large extent, it ties your implementation to their tools.

Equivalence checking challenges:
It is a well-documented issue that equivalency checking is a weakness of the <vendor>Ware solution. Vendors normally provide a behavioral model for functional verification as well as logic equivalency. This model is different from the synthesis model used internally by the tools and hence there is always a chance for non-equivalency issues.

ECO difficulties:
  Another aspect of <vendor>Ware that can present challenges is that of ECOs since the synthesis model is, from a user perspective, a black box hence making it difficult (or impossible in some cases) for a user to implement and verify an ECO.

It is unnecessary!!! 
Modern synthesis tools have addressed the original challenges, and coding without the use of vendor<Ware> allows the tools the greatest degree of flexibility to optimize. Modern synthesis tools can perform complex CSA transformations, speculation, and many other optimizations. By keeping coding at a higher level, the tool has more flexibility to optimize in the context of the overall design goals and the surrounding logic and therefore yielding better results. A frequently overlooked aspect of <vendor>Ware is highlighted by "DesignWare minPower" - the original <vendor>Ware was not created with power in mind so now you have to manually choose if you want the version that gives the best area or the one that gives the best power. Higher level constructs do not have this issue since the tools will optimize according to the goals specified by the user as well as the context of where it is used.

The main benefits of avoiding <vendor>Ware are:

  • Ability to use traditional EC & verification flows
  • No linkage to any specific vendor or tool
  • Ability for tools to fully optimize resulting in better Quality of Silicon
  • Goal-agnostic implementation of the target design
  • Portable code (across technologies, tools, etc.)
  • Reduction in legacy issues
  • Increased ability to implement ECOs

Please send me your comments and questions if you have any.

Good luck with your project.


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