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How to Pick a Synthesis Tool - The Right One for You - Part 2

Comments(2)Filed under: Logic Design, Synthesis, RTL compiler, methodology

By Kenneth Chang, Core Comp AE, Team FED.

In my previous blog, I had written about how "Synthesis matters."  Snippet below.

<snip> I had a boss that once said that all synthesis tools are same.  This guy knew his stuff, been in the industry forever.  He said "synthesizing with Tool X may give different results from Tool Y, but once it gets into P&R, it was all the same, P&R will take care of the rest."  In a heavy benchmark, I proved him wrong.  Synthesis does matter (and I'll give more details in a future blog). <snip>

Now, why does synthesis matter?  Isn't a netlist just a netlist?  Who cares right?  Doesn't P&R tools just fix the synthesis netlist as long as it meets timing, make it all fine and dandy in the end anyways?  Specifically, what can synthesis Tool A give that Tool B can't?  The key is, it's not about just Tool A vs. Tool B.  It's about an entire design flow.

We always talk about garbage in garbage out.  Literally, if you feed garbage into your P&R backend tools, you will get garbage out.

So, let's define garbage designs.  These are designs that are over-constrained.  These design have become over-sized because of so called 'intelligent' margin built-in by over-clocking the design.  Margin your clocks by 15%-30% to make sure you meet timing in the backend - right?  Not a good idea.  Now you pass on some headaches to your backend team.  Maybe create congestion issues which may not have happened if you didn't add these extra budgets.  Even worst, maybe your design won't fit in the floorplan that was created for it.  Great, now you have to change or grow your floorplan.  Hopefully, you don't have to grow your die.  I've seen this before having been a designer before joining Cadence ... which is why I believe synthesis matters.

Now let's define quality designs, with a seed netlist that matters for P&R work.  These are desgins constrained as specified.  No extra clock margining needed, so the design created is as expected.  This synthesis netlist is received by the P&R tools with open arms.  At this point, this honest netlist goes through transformations in the backend if needed, where it should happen.  Buffering, increasing cell drive strengths, some restructuring.  Quality in, quality out.

So, the key to success is picking a synthesis tool that will give you the best end P&R results.  It shouldn't be measured after just synthesizing with Tool A or Tool B.  RTL Compiler is architected to help achieve this goal.  (for more aggressive needs, there has always been the discussion and the option of using physical synthesis, for example, with RTL Compiler Physical, which takes this a step further with even better correlation up front to backend results)

Synthesis does matter.  So pick your tool wisely!

Kenneth Chang

Comments(2)

By Sanjay on July 13, 2009
Kenneth,
I have done enough benchmarking on various complex designs using different synthesis tools such as Get2Chip now RC, DC/DC-Ultra, Ambit-PKS, DC-Topo, Physical Compiler. I agree with you that quality of netlist matters most to backend tool.
But I don't think you can hand-off netlist with 0 margin to backend tool. If it is timing critical design and you don't synthesize with margin it simply won't meet timing after layout, period!
I also think floor plan and die-area will be more if netlist going to P&R doesn't have margin.
Final point, as far as I know from most of the backend engineers, Encounter and other backend tools don't optimize design as much as DC and RC does.
Sanjay

By Kenneth on July 16, 2009
Hi Sanjay,
Thanks for your feedback and sharing your experiences.  I have also used all the tools you used before I joined Cadence as a designer.  I agree with you, I've seen that if I didn't overconstrain using non-RC synthesis tools, my design sometimes wouldn't meet timing in the layout.  It had been like that for a long time.  However, whenever this overconstraining was needed, there was always a price, where it usually caused designs to blow up in size (my usual first care about for particular designs) if things are tight.  I've seen so many designs grow because of overconstraining.  Not just small growth, huge grow, as bad as 20-30% if you're not careful, because the tools works hard to make it work (I used to experiment with overconstraining to find the sweet spot for my synthesis tool for particular designs to meet my needs).  What then happened was that the backend designer told me to reduce the size (because I could see so many cells were being upsized with x8, x16 ...  very little x1 drive strengths, and lots of buffer insertion, or alternatively the backend person would need to grow the floorplan.  In some cases, growing the floorplan wasn't an option.  The issue is when the growth of the design has already happened, which drives the floorplan, which might not be good if it wasn't necessary to overconstrain to begin with (and maybe result in a smaller floorplan).  With my experiences (and collegues including R&D) with RC, by nature of the way it has worked for the last while, it is tuned to give best results when the target is set realistically with no margining in manipulating the clock period to be smaller, even on the tougher designs.  For the backend tools, I agree, I've heard the same thing (and makes sense), these tools typically don't optimized as much as synthesis tools do(for one thing, it can't start with the RTL source to make major structural decisions up front of course).  If the design is really tight, this is where physical synthesis may help such as with RC Physical.  If you haven't heard about it, you can find some info on this datasheet link:   www.cadence.com/.../encounter_rtlcompiler.pdf

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