By Kenneth Chang, Core Comp AE, Team FED.
In my previous blog, I had written about how "Synthesis matters." Snippet below.
<snip> I had a boss that once said that all synthesis tools are same. This guy knew his stuff, been in the industry forever. He said "synthesizing with Tool X may give different results from Tool Y, but once it gets into P&R, it was all the same, P&R will take care of the rest." In a heavy benchmark, I proved him wrong. Synthesis does matter (and I'll give more details in a future blog). <snip>
Now, why does synthesis matter? Isn't a netlist just a netlist? Who cares right? Doesn't P&R tools just fix the synthesis netlist as long as it meets timing, make it all fine and dandy in the end anyways? Specifically, what can synthesis Tool A give that Tool B can't? The key is, it's not about just Tool A vs. Tool B. It's about an entire design flow.
We always talk about garbage in garbage out. Literally, if you feed garbage into your P&R backend tools, you will get garbage out.
So, let's define garbage designs. These are designs that are over-constrained. These design have become over-sized because of so called 'intelligent' margin built-in by over-clocking the design. Margin your clocks by 15%-30% to make sure you meet timing in the backend - right? Not a good idea. Now you pass on some headaches to your backend team. Maybe create congestion issues which may not have happened if you didn't add these extra budgets. Even worst, maybe your design won't fit in the floorplan that was created for it. Great, now you have to change or grow your floorplan. Hopefully, you don't have to grow your die. I've seen this before having been a designer before joining Cadence ... which is why I believe synthesis matters.
Now let's define quality designs, with a seed netlist that matters for P&R work. These are desgins constrained as specified. No extra clock margining needed, so the design created is as expected. This synthesis netlist is received by the P&R tools with open arms. At this point, this honest netlist goes through transformations in the backend if needed, where it should happen. Buffering, increasing cell drive strengths, some restructuring. Quality in, quality out.
So, the key to success is picking a synthesis tool that will give you the best end P&R results. It shouldn't be measured after just synthesizing with Tool A or Tool B. RTL Compiler is architected to help achieve this goal. (for more aggressive needs, there has always been the discussion and the option of using physical synthesis, for example, with RTL Compiler Physical, which takes this a step further with even better correlation up front to backend results)
Synthesis does matter. So pick your tool wisely!