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Now Available: RTL Compiler 9.1.100

Comments(1)Filed under: Logic Design, RTL Compiler 9.1, RC-Physical, RE-Spacial, PLE

I'm pleased to announce that our latest version of RTL Compiler - version 9.1.100 - is now available.  This release is a significant upgrade for RC users, I would encourage all our customers to check it out as soon as you can.  Some of the highlights include:

Quality of Silicon improvements.  For timing-critical designs, we have seen some pretty good improvements in terms of performance and area.  Yes, this holds up in physical design as well.

Capacity improvements.  On average, this release shows an average of 30% reduction in memory consumption.

Native congestion analysis, fixing, and prevention.  Congestion is now modeled natively inside RC-Physical.  This enables more automatic optimizations for congestion, which is a very localized type of problem that you do not want to address uniformly across a design.  For more on that topic, please check out our congestion whitepaper.

RC-Spatial technology.  The next generation of our physical layout estimation (PLE), RC-Spatial uses rapid placement to better estimate long wires in your design.  This helps deliver more accuracy to the core synthesis optimization engine during RTL-to-gate synthesis.  Since this is new technology, be sure to use the latest USR of RC when using it.

Sequential merging.  RC now merges equivalent flops or latches by default.  This conserves area, easing place & route, and reduces the overall clock load, which reduces clock tree power.

Multi-bit cell inferencing.  This has been added in stages over the past year, having been completed in 9.1.100.  For target libraries with multi-bit sequential or combinational cells, this optimization can save area as well as capacitive loading.  The impacts on DFT and optimization are considered automatically by the core engine.  This needs to be turned on with an attribute.

Incremental retiming.  Retiming can now be performed as an incremental optimization to improve performance, area, or power.  It even works in the RC-Physical context, and RC-Physical will incrementally re-place the retimed flop.  This feature, available in all RC packages, is enabled with an attribute, and offers fine-grained control over what it applies to.

CPF-aware RC-Physical.  RC-Physical can now utilize CPF information to perform legal placement, cross-domain optimization, and legal incremental placement within power domain boundaries.  This offers deterministic design closure for multiple power domain designs.

RTL Design Explorer.  If you are looking to reduce active power consumption but are hesitant to try reducing voltage levels because you do not want to miss your performance targets, there is a new automated way to explore all the different voltage level combinations for your power domains.  You can quickly see which  approach best satisfies your overall design goals, then use the generated script to take it forward through production top-down multi-supply multi-voltage (MSMV) synthesis.

RC Quality Analyzer.  We have built into RC a full design checking capability.  It can run at the RTL or gate-level, checking rules such as RTL lint, DFT, low power structures, constraints, clock domain crossing, and even library consistency.  This is even a platform from which you can run advanced capabilities like Conformal Constraint Designer's false or multi-cycle path validation.

GUI improvements.  First, the GUI response time has been sped up by an average of 10x.  There's a lot of advanced analysis capabilities available in the RC-GUI that can help with visualization and debugging, I encourage everybody to take advantage of them in your next synthesis run.  Also to that end, we have activated the GUI during batch runs.  So you can "raise" the GUI from the command-line to analyze something, then "lower" it back out of sight to return to batch mode.

Command to determine worst PVT corner.  Multi-corner analysis and optimization has become more critical in today's process geometries.  However synthesizing for multi-corner is expensive in terms of runtime.  We have added a command that returns the worst timing corner for a library, so you can synthesize for that corner.  This allows you to optimize timing for the true worst corner, without the added runtime overhead of multi-corner.  This is in addition to the power_library capability we have had for years - which allows you to specify an additional library for power analysis and optimization to go along with your timing library.

DFT.  The R&D team has done a lot of work to make DFT seamless inside of RC.  Now that they have accomplished that, they're starting to add some new capabilities such as advanced rule checking, deterministic fault analysis and test point insertion, support for AC test (IEEE 1149.6) for designs with high-speed IO blocks, and automated compression analysis to determine the best compression ratio.

Wow, that was a long post.  As you can see, there are a lot of new capabilities.  This was a brief overview of each.  In the coming weeks, we will have some of our technical folks provide more in-depth posts describing each of these.

As we start planning our future releases, do any readers have any suggestions?


Jack Erickson
Product Marketing Director
RTL Compiler Synthesis

Comments(1)

By DMK on July 6, 2009
I am looking for a possibility to use VHDL files inside OrCAD. Can you help me?

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