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Don't Let Power Kill Your Project - What % LVT Should I Use?

Comments(0)Filed under: Logic synthesis, Low power , Logic Design, power, blog logic design, power design, battery, synthesis RTL Compiler methodology logic design, power management, logic low power design, low power design, Synthesis, leakage power, cadence, logic desgin, FED, TeamFED, synthesis methodology, Diego Hammerschlag, multi-vt

By Diego Hammerschlag
Sr. Technical Leader
Team FED

A common question or requirement that designers have is the percentage of low voltage threshold (LVT) cells that should be allowed in a design. For those not familiar with LVT cells, they are special cells that have a lower voltage threshold and can therefore switch faster while maintaining the same footprint. The gotcha of LVT cells, since you know there always is one, is that lower voltage threshold means a higher leakage current which in turn translates to substantially higher leakage power. As a result of the increase in leakage power, their usage is almost always limited.

In many cases, I have seen design teams abide to hard rules regarding the percentage of LVT cells allowed in a design. Not sure what got the practice started, but seems counter-intuitive considering that the actual goal is improving power and/or performance. One would think that a lower percentage of LVT cells mean that leakage power is better, possibly at the expense of performance. This is indeed a misconception. There are several cases in which the amount of logic increases considerably, while keeping the percentage of LVT cell low, or even not using the LVT cells altogether. The obvious problem is that a large increase in design size and cell count would almost certainly have severe effect in overall power. In addition, significant increases in area and cell count could affect routing and ultimately result in a variety of serious physical design issues.

So what percentage of LVT cells should be used? Well, the bottom line is that there is no reason to use an artificial metric such as percentage LVT cells. If you know that your goal is, for example, leakage reduction, use your leakage power target as an indicator. After all is pretty straight forward to measure and report in today's synthesis tools. Do not let guidelines such as this prevent you from leveraging the full value of techniques such as top-down multiVT optimization.


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