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The Dangers of Excessive Guard Banding

Comments(0)Filed under: Logic synthesis, Logic Design, Physical timing closure, synthesis RTL Compiler methodology logic design, logic low power design, Synthesis, QoS, Matt RardonBy Matt Rardon
Synthesis Solutions

I want to take a couple of minutes to talk about guard banding of constraints in logic synthesis. This approach was initially conceived to add a little bit of padding to the design to account for inaccuracies in synthesis modeling techniques and to provide some wiggle room for downstream tasks such as clock tree synthesis. The guard band was typically 5-15% of the clock cycle. This approach worked well since the small margin was within the capability of the sizing based optimization algorithms in place and route tools. Over time as geometry size has decreased, the use of guard bands has become more of a crutch for poor wire length estimation techniques (i.e. wireloads) and, therefore, the degree of guard banding has become excessive.

When a guard band is used you are essentially telling the tool to be x% pessimistic on each and every path. If you have use an excessive guard band of say 35% then you are building 35% of pessimism into every endpoint. This may not be enough for some paths and will certainly be too much for others. For example, is the guard band sufficient for critical paths or for paths with very deep functions such as datapaths? Is the guard band overkill for the vast majority of the paths in the design that are not critical? Not to mention that an excessive guard band can have the effect of unnecessarily increasing the power consumption of the circuit.

The use of an excessive guard band means that the place and route tool is faced with the challenge of resizing, or right-sizing, the entire design once the actual wire lengths are known. This may require a lot of upsizing on critical paths and a lot of downsizing on the huge number of non-critical paths. Place and route tools are designed for localized resizing, not the global types of transforms that would be required to recover from excessive guard banding. Not to mention that the resizing step in a place and route tool is performed after placement. At this point in the flow the goal is to not perturb the placement unnecessarily. This of course means that the scope of the optimization will be necessarily limited.

A synthesis tool is much better equipped for this global type optimization. For example, a synthesis tool is a much better vehicle for gate composition, decomposition and other mapping decisions. And the quality of this global optimization is going to be highly dependant on the quality of the net length estimation. The quality of the netlist going into place and route does matter. A netlist that is right-sized during synthesis will result in a more optimal initial placement and will be ideally suited for the resizing based operations that are required to close any remaining timing issues. This is exactly what the PLE (Physical Layout Estimation) was designed to do.

The PLE addresses the short comings of traditional net length estimation techniques used in synthesis. Therefore, the use of excessive guard bands is not necessary. In fact, the PLE allows the designer to use a guard band in the way that it should be used - to provide a little bit of padding.

Give the PLE a try! All you need to do is import the physical library (LEFs and capacitance table) into RTL Compiler and synthesize as you normally would.


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