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Can’t Wait To Try Power Management in the New InCyte Release?

Comments(0)Filed under: Logic Design, CPF, chip planning, power management, chip estimator, ChipEstimate.com, C2S

Coming up next week are several techtorial events, called "System-level Design & Chip Architecture for Low-Power ICs Techtorial and Workshop". Yes, that's a keyboard-full of words. But the concept is simple.

The main focus is on Power  –   from system-level to chip architecture.

From the perspective of planning the design early, you'll experience how to trade-off the costs/benefits of power-saving techniques for your design. After you experience the hands-on session, you'll be confident you can make high-impact power management decisions for your design.

Dates and Location

  • April 7th in Irvine
  • April 8th in San Diego
  • April 9th in San Jose

Check out the full agenda, locations here.


++ Mike Carrell

p.s. Trivia answer... A rookie wookie. (Answer from my last posts trivia question)


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