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When Do You Know You've Saved Enough Power?

Comments(1)Filed under: Logic Design, PSO, Power Shut-Off, ARM, RTL compiler, MSV, DVFS

This guest post is by David Weir, Lead Design Engineer at Cadence.  His paper, "When do you know you've saved enough power?" was voted best-in-track for Logic Design at CDNLive! 2008 Silicon Valley.

In this paper we set out to show how designers can measure and explore the impact of implementing different power schemes in their designs.

Ultimately this allows us to trade power consumption, performance and area against each other to optimize the design for the end user.

We talk about how it's often the case that the power intent is only applied after the RTL is created  (like when designing the derivative products or those that license 3rd party IP).

This can lead to some interesting questions about how the logical hierarchy should matches the physical layout, how the timing critical paths change as you port the same design to different libraries and how you might need to explore multiple power intents to get the best overall product.

It was fun to write and present this paper - folks came up with some really good questions on the day. I hope you enjoy reading it!

https://www.cadence.com/cdnlive/library/documents/2008/Silicon%20Valley/3LD12_David%20Weir.pdf 

 

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David Weir

Comments(1)

By Gail Haley on December 29, 2009
Is this the David Weir that worked for Motorolla in Australia?

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