I always get this wry smile on my face when I see it happen. An effort that is launched with lofty ideals and worthy goals, but with those predictable pitfalls that will, in the end, park the car on the train tracks, just waiting for the next locomotive (driven by someone of impure motives) to blast the dreams right off the tracks. With act one firmly in the books at this point (the car is positioned), it will take significant efforts to ensure that onrushing train does not reach its target prior to pushing things back onto the road. Another one of those predictable melodramas? Maybe, maybe not. The outcome in this case is not so certain. It will take a concerted effort to prevent the disaster though.
All metaphors aside, the ratification of IEEE 1801, formerly Accellera Unified Power Format, has been ratified. Some great work was done to evolve the format into a production-worthy set of semantics, such as moving from a net-based to a domain-based semantic. Like Si2’s Common Power Format, which has a couple of years as a standard in full flow production usage at this point, 1801 set out with the original goal of unifying the description of the power strategy for SoC’s into a single, golden file that could be used throughout the design, verification and implementation processes.
However, around final balloting time, when the troops were perhaps a little battle weary, a curious turn of events transpired. One of the original tenets of the work, the goal of a single golden, unified description of the power strategy for a chip, was set aside in the name of “progress” towards ratification. Provisions in the standard were made to “de-unify” the power strategy specification. The original stated objective was to unify the description of voltage domains, isolation logic, level shifters, which registers should retain state, the different power states of the chip and the transitions between them. With a single improbable maneuver in the last throws of ratification the entire concept of “unified” has been lost.
The divergence from the simplicity of an aggregated power strategy description in a single, golden file, to the hide and seek anarchy of spreading the strategy across functional (HDL), constraint (SDC), library (LIB), and power files (UPF) could ultimately be a death blow to interoperability. More importantly, it fundamentally adds an unnecessary element of complexity that will undoubtedly lead to delays in project schedules and chip failures.
Essentially what has transpired is that the standard serves as a public communication of proprietary methods. While you could argue that this is an improvement over the past, it is so far from the original ideal that you really ought to be scratching you head at this point. Why? Why would they do this? One committee member, an IP provider, confided to me, with a shrug of the shoulders as if to say “that’s life”, that they would never use the format in that disaggregated manner; therefore it was not a problem to them. However it is a huge threat to the purpose of a standard – interoperability.
The perpetrators of this crime against design came adorned with excuses. One somewhat “priceless” claim was that it was being done in the name of saving the users of commercial IP users from themselves. What was really going on had a lot more to do with control than solving engineering problems. The owners of the “de facto” standards seek to broaden their silent stranglehold on design data to continue to leverage it in the hopes of holding users hostage via format rather than capability.
It ought to be with religious-like zealousness that the design community responds with outrage. From the outset it was chip designers, library vendors, foundries, service companies all agreeing that an aggregated power strategy specification was the best approach. Interoperability is not being served. The larger challenge of advanced low power design is not being served. It seems that, at this point, only a selfish agenda is being served.
They were so close to getting it right. What can be done at this point? It will take a concerted collaborative effort to ensure that the “working subset” of IEEE 1801 is the unified elements of the standard. A de-facto standard within the standard will be needed to ensure that the promise of interoperability and the challenges of low power design can be maximally addressed. If not, it may be well that case that the locomotive reaches its target and we all look back, holding our thumb and forefinger an inch apart and say, “well, they were that close to getting it right”.