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New Features In CPF 1.1

Comments(0)Filed under: Low power , CPF, Qi Wang, IP, MMMC, DVFS

This is a guest post by Qi Wang, Sr. Architect for the Cadence Low Power Solution, providing more information on what is contained in the recently-announced CPF version 1.1.

There are many major improvements in the new Si2 CPF version 1.1, and I would like to provide more details on a few of them:

  • Complete hierarchical flow support
  • Complete IP reuse support
  • Consistent modeling of low power cells from RTL to GDSII using secondary power domain
  • Full support for DVFS design verification and MMMC implementation
  • Support for disjoint power domains
  • Equivalent control signals

Hierarchical Flow Support

CPF 1.1 has all the syntax needed to create a complex low power IP and integrate it into the top level design by using the powerful new concept of power domain mapping. Power domain mapping specifies how a IP level power domain should be integrated into a chip level power domain. The same specification is used for RTL power-aware simulation, power-aware logic synthesis, physical implementation, sign-off analysis and low power verification. It not only enables seamlessly handoff low power IP's between design teams but also enables closed-loop verification of low power designs in hierarchical flows.

IP re-use support

There are two major enhancements in IP re-use support. First is support for parameterized low power IPs. This enables IP vendors to create a single low power IP to be used by different users with different power configurations, depending on their specific needs.

Second is the introduction of CPF macro models. CPF macro models are a unique way to model any low power customer IP, such as dual-rail RAMs or flash memories, multi-rail analog blocks etc.  It not only has the syntax to describe the low power structure of the IP using only the boundary pins of the IP, but also has the semantics to drive the simulation of such IPs at the block level as well as chip level. Traditional low power IP validation only takes place at the block level. With the CPF macro model specification, low power custom IPs can also be simulated and verified at chip level along with the low power features at chip level by combining the macro model CPF with the chip-level CPF files.

Secondary Power Domain

Many low power cells - such as always-on buffers, retention cells, and isolation cells - have two power supplies.  The new secondary power domain concept enables modeling of such logic even at the RTL.  Additionally, using the same specification, implementation tools can automatically connect the correct supply nets to the secondary power or ground pin of such low power cells without any user intervention.

This not only simplifies the flow and eliminates the possibility of human error, more importantly it ensures that the implementation tools implement exactly what has been verified at RTL using the same CPF specification.

Disjoint Power Domain

In real designs, an RTL or logical-level power domain may have to be implemented into different physical regions with unconnected local power supplies. Such implementation of a power domain is also called Disjoint Power Domain.

CPF 1.1 allows specification of such implementation details later in the design cycle while maintaining the RTL power domain specification as the golden reference. Implementation tools can use the disjoint power domain specification to drive physical implementation while verification tools using the same specification to check for the correctness of power connections upon the physical netlist.

Equivalent Control Signals

In low power designs, there are many control signals to control low power features such as power gating, state retention and isolation. Typically, a single control signal is used to turn on or enable a set of devices. However in very large designs, such control signals may fanout to thousands of loads. To control the rush current due to the simultaneous turn-on of all connected devices, designers typically use time-staged control signals to turn on the devices group-by-group. Such control signals are called equivalent control signals with respect to the master control signal. CPF 1.1 allows the specification of the master and equivalent control signals at RTL to enable RTL simulation of such designs. The same specification is used to drive implementation to optimize the fanouts of each control signal, depending on the physical placement. Verification tools use the same specification to check the correctness of the implementation of the control logic.

Full Support for DVFS Design Verification and MMMC Implementation

CPF 1.1 is enhanced to model the power mode-specific domain transition time of any general dynamic voltage-frequency-scaling (DVFS) design. This specification can be used for RTL simulation of the design with sophisticated real delay models to simulate the dynamic behavior of a DVFS design.

The same specification can be later on refined to setup multi-mode multi-corner (MMMC) analysis and optimization at the implementation stage.

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