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Are You Guilty of "Synthesis Inertia"?

Comments(0)Filed under: Logic Design, rtl compiler 8.1, synopsys, rc, tcl, synthesis methodologyBy Jason Ware
Sr. Technical Leader
Team FED

Inertia is the resistance of an object to a change in its state of motion. (Wikipedia).

Are you guilty of staying with synthesis scripts that were written when we were still in the Cold War? Well, maybe its time to "tear down the wall" and start fresh with a new synthesis methodology. I know, it works, so why change it? Its hard to find the time to re-write scripts that have worked for you for many years, besides, with the recent layoffs, maybe the person who wrote the original scripts is no longer around. How can you overcome this inertia?

Well, maybe what you think "works" actually doesn't, that is when you consider you may be leaving timing, power, area and runtime on the table. I recently worked with a customer who, using a corporate developed script with a competitor synthesis tool, saw his runtime drop from over eight hours to just 20 minutes with Cadence RTL Compiler (RC) and a fresh script.

RC is based on a completely different synthesis methodology than competitors based on Berkley synthesis developed in the 80's. Because of this, runtime and capacity are much greater allowing for less scripting and a "top down" synthesis methodology.

Moving to RC scripting is even easier if you consider RC's "write_template" command that builds the script for you. All you do is plug in the library, RTL and constraint locations.

rc> help write_template

write_template [-split] [-no_sdc] [-dft] [-power] [-full] [-simple] [-area] [-retime] [-n2n][-cpf] [-multimode] [> -outfile string] [-yield]

 So, time to slow down the big ship with a small rudder and move to a more agile method of synthesis. Your local RC AE's can get you started.


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