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Build ASICs With a Strong Ecosystem: A New Paradigm

Comments(0)Filed under: chipestimate, ASIC, logic design, ChipEstimate.com IP portal Cadence ecosystem, IEC, designvision, Engeneering Consortium

Building ASICs is a pretty much standard process - you may define your specification based on whatever constraints you have, pick your IPs if any, do a guess-timate of your entire chip so you can figure out the budget, then commit - plunk down the cash and commit resources so you can really do the work to get silicon out the door.

What hasn't been standard is the way people have approached doing something like the above.  Specifically, beginning with the specification, every company project group may have their own way of manually, semi-automating, or almost-fully-automating the above process so that things can get done faster and more accurately in order to meet their schedule needs and utlimately the market window for their product.

A key recipe ingredient that many companies have shared with me is the importance of ensuring the IP portion of the ASIC ecosystem is strong.  This includes:

  • Availability
  • Accessibility
  • Flexibility 

A wise man (Camille from IDT) once told me - IPs and the strategy around them are integral to building successful ASICs.  Lots of companies now base their designs on some IP.  In fact, he even wrote a paper related to this IP stuff that was published late last year to back up his passion which he shared with me.

So comes the next question: how do I create such an infrastructure to create this beautiful ecosystem / playground where I can build and prototype ASICs earlier with higher ease?

One answer is to in part turn to tool automation.  Check out ChipEstimate.com for more details. This large ecosystem of IP as well as their tool leverages the 200+ IP vendors and foundry relationships, providing thousands of popular IPs, probably at least some you are already using.  The tool cockpit also allows you to define your own internal IPs easily, pretty cool stuff.

ChipEstimate.com in fact has been so well received by customers in the last year that it just won 2009 DesignVision Award from the International Engineering Consortium (IEC).

Here's a short clip of the ChipEstimate guys collecting their award and Adam's (aka as 'the young boss') speech:



If you're looking to improve your ASIC decision-making process up front, definite check out this stuff to at least get ideas for your next project since it is very useful and practical.


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