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Freescale Power Management Chip Tapeout

Comments(0)Filed under: Logic Design, low power design, Fujitsu, Steve Carlson

Another newsworthy item has hit the wires, of course this one is from Cadence.  Now I know you're thinking to yourself, "what's the big deal, another press release from Cadence touting its products".

http://www.cadence.com/cadence/newsroom/press_releases/Pages/pr.aspx?xml=012009_freescale

Well, yeah.  But the good bits tend to be really subtle in the context of a press release; in this case they're all buried in paragraph 3:

  • Multiple supply -  this is a big-hitting technique for reducing active power that is under-utilized. If you reduce the voltage, it reduces power by a squared factor.  Why doesn't everybody do that?  Because it also slows down performance.  The trick is to figure out where you can do it, and also how to optimize paths between voltage domains.  Not to mention the implementation constraints associated with placement in domains, powering those domains, and connecting them properly with level shifters.
  • Power shutoff - this is another big-hitting technique, but for reducing standby power.  This adds functionality overhead, yes.  That needs to be verified with extra tests, and of course you want to make sure other activity does not accidentally interact with the power shutoff logic.  But our simulator handles it natively so simulation overhead is zero, other than the extra tests you have to run.
  • Multiple modes - almost all chips today have multiple modes to some extent.  Since this seems to be a single-function chip - power management - the multiple modes are most likely associated with having certain blocks powered off.  But there are lots of chips that actually have multiple functional modes with different timing constraints, which is why synthesis and implementation tools need to be able to optimize for multiple modes simultaneously.  It's very complicated trying to manually budget to satisfy multiple modes.
  • Mixed signal -  mixing of analog and digital is becoming more prominent, and analog circuitry is more power-dense.  So all this talk about low power really needs to include mixed signal from now on.  As you can see here, this not only requires support in the tools and methodology, but also the process and most likely the IP.  Not simple, but necessary.

All of that, captured in the middle section of a press release that most people would think at first is boring.  There's a lot going on here!  Even the quote at the end, by Steve Carlson, at first may not sound exciting.  But I guarantee that if you catch him talking about this in person, it will be inspiring!

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