Home > Community > Blogs > Logic Design > why should i use a floorplan for physical prediction and synthesis

 Login with a Cadence account. Not a member yet? Create a permanent login account to make interactions with Cadence more convenient. Register | Membership benefits
 Get email delivery of the Logic Design blog (individual posts).

## Email

Recipients email * (separate multiple addresses with commas)

Message *

 Send yourself a copy

## Subscribe

Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.

First Name *

Last Name *

Email *

Company / Institution *

 Send Yourself A Copy

# Why Should I Use a Floorplan for Physical Prediction and Synthesis?

Comments(0)Filed under: Logic Design, incyte, Synthesis, QoS, Floorplan, chip estimator, Physical Prediction

It goes without saying that performing logical synthesis without timing or power constraints is of limited value at best. The netlist that is painstakingly crafted by a synthesis tool is very much tied to a particular set of constraints. Cell function and sizes have been selected to meet the timing targets and cell power and VT attributes have been considered in order to meet the power targets. Logic cones have been iteratively optimized to meet these targets. Taking a netlist that has been generated using a specific set of constraints and applying a radically different set of constraints will certainly result in poorer than expected Quality of Silicon as compared to generating a netlist from scratch using the second set of constraints.

So why would performing physical prediction and optimization without a floorplan fare any better than performing logical synthesis without adequate constraints? A floorplan is certainly a constraint for physical implementation. The same holds true for physical synthesis. At the most basic level, a floorplan sets a limit on the amount of real estate that is available for a design. The die size and the associated aspect ratio dictate the dimensions of the silicon. This is a constraint on the maximum size for a design. It is also a constraint on the nature of the net lengths since a tall skinny rectangular aspect ratio will have a very different net length distribution than a square aspect ratio. The port and hard block locations specified by the floorplan will certainly impact cell placement estimation as well as the net length estimation. The cell structure of a path going from a port to a RAM on the other side of the die will be quite different from the structure of path going from a port to a near by RAM. The list goes on and on. Placement and routing blockages will affect the nature of the placement and the layout of the net routing which will in turn affect the path delays. Placement regions will dictate the geographical location for associated logic which will affect the length of the intra-block and inter-block nets. The location and size of the power domains will certainly have an effect as well.

Just as traditional synthesis constraints evolve and are refine during the design process, so too can evolve the constraints supplied by the floorplan. Early in the design process a die size may suffice. As the design becomes more concrete, additional constraints such as port and hard block locations can be specified. Further design refinement and analysis may show the need for placement guides. The end result is the detailed and optimized floorplan that is used for the physical implementation.

Each design process is a bit different so it would be great to hear about some that are in use. How early are the block or chip die size and aspect ratio available in your design flow? Where does this initial estimate come from? If you’ve been asking yourself this same question then you may want to give InCyte Chip Estimator a look. It is ideal for this. How early is port and block placement information available in the design flow? In your experience, how often is the floorplan updated during the design flow?