Being both old and an engineer, I’m cheap. I really like free stuff.
So, here are a few things you might find useful. And free.
Si2 has just recently approved Common Power Format (CPF) v1.1. This represents the third generation CPF standard, incorporating lessons and requirements learned over the past two years. Some significant enhancements include support for IP development and reuse (both hard and soft), secondary power domains, macro modeling, assertion control, improved mode transition control, pin/power domain association, and many more. The freebee here is the CPF v1.1 Pocket Reference. While I’m at it, I’ll throw in the CPF v1.1 spec.
Low Power design has a lot of nuances and subtleties. For example, how should assertions be handled in a power down domain when the power is cycled? What sort of formal verification strategy should be used to ensure that there are no power off cells on power control nets? How should test be structured so the die doesn’t burn up on the tester? And a lot more things like this. Fortunately, people have been down this road and have uncovered and solved some of these issues. The Power Forward team has collected a set of experiences into a guidebook – A Practical Guide to Low-Power Design. This includes chapters written by major LP players, including Freescale, NXP, ARM, ARC, and many others. There are also sections describing LP verification, design, implementation, and test – things to be careful of, and things to manage. And there are new chapters being added all the time. All you have to do is to give them your email address.
There have started to be some useful utilities started for power design. Maybe one reason why there aren’t more is the availability of a power intent parser. Well, Si2 has a CPF v1.0 parser available for free – just click here and you can get started. The stated purpose of this is to jumpstart the creation of products and tools. If anyone knows of a publicly available UPF parser (Accellera, IEEE, or other), let me know, and I’ll post that link here too.