Day 2 @ CDNLive San Jose: Another interesting day - met quite a few people, some new, others I met the day before while co-presenting at two morning sessions, and also some of my fav customers. My focus-of-the-day - ChipEstimate awareness with a touch of RC-P.
Here are some attendees' feedback:
Question: Huh? ChipEstimate? What is it? Just an IP portal and some floorplanning stuff? What's so special about that?
Question: New tool? Sorry, never heard of it.
Question: Is ChipEstimate STILL ChipEstimate post-Cadence purchase? (keep it that way please)
Question: Very cool! I'm in. By the way, are you sure the young lookin' dude over there in the white shirt used to be the CEO?
... so. What is ChipEstimate? First, it's an easier way to get IP information at your finger tips. Lots of people complain of: (1) having to making many phone calls and emails when they're looking for IP, and all the research - where do you start? (2) even after they do this, information comes in painfully slow sometimes, and even worse, and this could involve all the unnecessary interaction with IP sales people before you have the data, which at times could be annoying if you like to just get the data (detailed enough) and study it first in peace (3) even after you get the data, it can be painful to extract all the information from datasheets and process it - too much work (4) 'what-if' analysis, like going from 90nm to 65nm, can be painful, etc ...
CE helps by providing the information more quickly and efficiently, giving you access to a huge database of products and vendors (in one cockpit), and with lots of flexibility. Database 're-use' is simply saving and restoring, making it very powerful for leveraging on future projects and 'what-if' analysis. Having been a lead ASIC designer before, and doing a lot of the above work, I really appreciate the value of this tool as both a time saver, and for making key business decisions early like "I will sign with my ASIC vendor because the sales person is honest, at least according to my CE database analysis" or "my chip is too big - I'm glad I didn't waste time building a chip with this configuration - it just wouldn't make ecomonic sense".
Second, CE is an 'early-floorplanner' for prototyping. It's easy to use and accelerates how you model all your design and IP (including lots of micro-details, not included here) into the big picture, and generates lots of useful statistics. Cool thing is that almost anyone can use this tool with ease: managers, CAD, designers, system architects. "Build-a-proto-chip-in-a-day" is definitely possible!
CE enables a "Concept-to-GDSII" flow - at least this is my terminology. You dream of your chip in building blocks as a system architect usually does (like, based on performance and other requirements, which microprocessor cores to choose and how many, what chip interfaces, what types of memories and how many, etc... basically the info you would send to your ASIC vendor when you initially engage at the early project stage, or for internal decision-making with your COT team), and convert your 'concept' into something 'real' including auto-creating a floorplan for backend tool use, before you even right your first line of RTL code. This is SWEET!
General response from attendees was positive.
Now my tidbit on RC-Physical. If you're interested in physical synthesis, check out the two presentations by Freescale and PMC-Sierra. I heard that the Freescale one was good. Didn't get a chance to get feedback on the PMC one yet. Too bad I couldn't attend either.
P.S. A few years ago, when I was working as a designer, I have to admit that I thought that CE didn't provide value. My boss asked me multiple times to download and try the software because it 'may' be useful, but I never listened and completed studying CE because I didn't think it would be useful. Looking back, I think I was wrong. :)
Below: ChipEstimate AE intensely giving demo using potential customer's own laptop in the 'common area'.