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Feeling Restless ... CDNLive San Jose Conference Update!

Comments(0)Filed under: Plan and metrics management, Formal analysis, Logic synthesis, Constraint design & validation, Equivalence checking, Static timing analysis, Logic Design, Physical timing closure, CDNLive

Ah yes ...  my first blog here!  I can't believe the freedom we're getting at Cadence, unfiltered blogging.  :)

I co-authored and helped deliver two presentations/papers yesterday with a couple of down-to-earth engineers.  Thanks to everyone who was able to attend these sessions, it was fun meeting y'all!

Here's a recap:

First session: Mark Lee from AMD shared their SDC constraints verification flow.  It was practical, large audience and lots of interesting questions.  (special thanks to Mark for making this happen)

Second session: Omer Ansari from Ubicom shared their ASIC flow experience in context of ASIC Vendor hand-off.  This took the approach of beginning with the 'ideal' ASIC flow with synthesis, formal verification, and STA (i.e. what the vendors tell you should generally work), what Ubicom REALLY did, and why.  Did migrating to completely Cadence tools flow feel trivial or did it break their flow?  Check out Omer's prez and paper for highlights. 

As a side note, one of my team members Buda Leung co-authored and presented some cool and innovative stuff with Broadcom on pro-active low power microarchitecture prototyping using C-to-Silicon, RC and ChipEstimate.  Definitely worth checking out.

Btw, thanks to Paul Little from Fujitsu who helped moderate these sessions and made it fun despite a touch of chaos. :)

P.S. CDNLive San Jose Agenda page for reference.


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