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Logic Design at CDNLive! Silicon Valley -- see you Sept. 8!

Comments(0)Filed under: Logic synthesis, Low power , Logic Design, Physical timing closure, CDNLive

We've been working hard to put together another CDNLive! event, coming up September 8-11 in San Jose.  There is a whole track dedicated to Logic Design.  Some of the events I'll be working at are:

Plus there are some interesting-looking sessions I hope to attend, like:

  • Sept. 9 at 3:05pm: Logic Design Technical Panel, which should be an interesting discussion around what the latest trends are in logical-physical handoff models.
  • Sept. 10 at 10:30am: Tape Out 65nm ASIC with RC-Physical in Six Weeks, where Allen Tsou from Cadence Services will talk about a some good experiences with RC-Physical on a customer project.
  • Sept. 11 at 10:00am: When Do You Know You’ve Saved Enough Power? , I think the title says it all, by the always entertaining and informative David Weir.  I try to make it whenever David is presenting...I always seem to learn something new from him.

Plus there's some others I'll it in on, so I'll be spending lots of time at the event.  I hope to see lots of you there!

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