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Some tips for predicting power consumption

Comments(0)Filed under: Low power , Logic Design, Physical timing closure, power estimation

In my previous post, entitled “How do you predict power?”, I was actually looking for reader input via the comments. 

I should have been more clear on that….perhaps I am too accustomed to my 6-year-old son, who will supply a barrage of responses to even a rhetorical question.  Anyway, I’d like to aggregate folks’ best practices for predicting your chip’s final power consumption.  A great place to start is this article, by my esteemed colleague, Brad Miller.Brad makes some great points in there, two of which I’d like to highlight.  First, getting accurate switching activity is a huge challenge that has no “easy” solution.  Re-using verification runs isn’t the best indication because those tests are designed to maximize coverage in the shortest amount of time possible.

If you were to re-use those runs for power consumption, your corner case scenarios would be nearly as equally-represented as your most common modes of operation.  Brad makes the point that if possible, capture vectors from system-level simulation, or hardware-assisted verification where you can run your actual software for long periods of time.  That way you get a large sample size of fairly-representative activity.
  The second point I’d like to highlight is accurate wire modeling.

It’s not necessarily that you’re looking to accurately capture the power consumption of wires (though they do contribute!), but really you want to capture the timing optimization behavior associated with realistic interconnect.  In other words, as you make a best effort at modeling your real interconnect, your timing-driven optimization tool (synthesis or physical implementation) will make the necessary transformations to your logic in order to meet your timing constraints.

And those optimizations often have a large effect on power.  Thus doing the best job you can at capturing realistic interconnect will not only help you more accurately measure power associated with your interconnect, but will also help you capture the power associated with the logic transformations that happen in timing closure.

Anyway, those are just a couple thoughts from me (and Brad!).  Please share yours in the comments section!

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