Home > Community > Blogs > Logic Design > how do you predict power
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Logic Design blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

How do you predict power?

Comments(0)Filed under: Low power , Logic Design, Physical timing closure, power estimation

You read stories about it – the device or chip that comes out and consumes more power than expected.  Maybe the battery life isn’t what it was supposed to be (my current smartphone is a great example!).  Or even worse, maybe there are failures because the excessive power density generates too much heat for the chosen package or heat dissipation method.  These stories get around because, well, product recalls tend to.
Of course, we don’t even hear about all the chips that were over-spec’ed for power.  Yes, given the above it is prudent to err on the side of caution.  But with a high-volume chip, the extra $1.00-$1.50 for the “safe” package or heat sink can really make a dent in the bottom line.
The root of this all is that these types of decisions are typically made very early in the project, long before you can test the chip in the lab to see what the real power consumption is.
As a logic designer, what can you do about it?  Is it even your problem?

To answer the latter question, it really has become everyone’s problem.  To be successful, you need to constantly measure it and refine the model, re-visiting those early decisions (product specs, package specs, project profitability, etc) course-correcting as necessary.  But what can you do about it?  The obvious answer is to measure it as early and often as possible.
But how do you get accurate power estimation during the logic design stage?  The software is going to have a huge effect that will vary over time – how do you account for that during logic design?  Physical timing closure has a large effect on power consumption – think about all those wire capacitances and all the cell swapping that goes on.  The clock tree often accounts for a large amount of power consumption….what do you do about that?
The problem is that you do need to know the answers to these questions as early as possible to make decisions such as whether to use techniques like power shutoff or multi-supply multi-voltage, etc.  You even need these answers as early as the decision-making process for what library, IP’s, and memories you will use.  As the project goes on, you can reduce the uncertainty more, and make adjustments as necessary.
But during logic design there is still a lot of uncertainty…it would be interesting to hear what folks do to reduce that.  How do you look ahead and get better power estimates while you’re doing logic design?  How do you make good estimates to drive the heat dissipation decisions?  And to the makers of my phone (not naming names!), how can you make adjustments for the next generation so the battery life is better?
I’ll roll up and post the best suggestions from the comments as well as some suggestions of best practices that we’ve seen out there.


Leave a Comment

E-mail (will not be published)
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.