Low power design has been a ubiquitous topic in the electronics industry the past couple years. The term "holistic" is often used (or over-used) to describe how you should approach low power design. I think the best illustration of how to approach low power design the right way to meet a customer's aggressive power specifications, is a recent interview that Cadence was able to do wtih Julien Buros, digital design team lead, for NemeriX.
Cadence: Please tell us something about NemeriX.
Julien: NemeriX is a fabless company based in the south of Switzerland. We develop low power GPS solutions, including hardware, software and firmware. We are entering our sixth year and our fourth generation of product.
Cadence: What is your customer base?
Julien: The boom of GPS started with the automotive market and is migrating into the cell phone market. Our customer base is still mainly in the automotive–oriented personal navigation device (PND) market, but we see stronger demand in the cellphone market where our low-power advantage is an important differentiator for our customers and consumers.
Cadence: Can you tell us a little more about why the market needs low power?
Julien: In the cell phone market—and handheld market in general—low power is a major concern. I guess we all expect that our new phone is going to have plenty of new features but we are not ready to charge the battery twice as often as before. When a new functionality—such as GPS—is added into one device, you have to make sure that it is not going to jeopardize the phone’s autonomy and negatively impact the whole user experience.
Cadence: Can you explain your general design strategy for low power design.Julien: Physical implementation is one part of the puzzle, but what we do is to take low power as the main criteria in our technical decisions, so it can be at the software level, at the RTL design level and at the application level.
The general strategy is to consider low power as the number one priority at every step of the design. To be as power efficient as possible takes a lot of multi-disciplinary skills. For example, the engineer who writes software needs to have a very good knowledge of what is in the hardware and how he can make best use of the low power features that are included on the hardware. On the other hand, the engineer designing the hardware has to know exactly what the software requirements are so that he does not over-design the product and put in features that are not going to be used or that do not make sense from an application point of view.
This may sound like a marketing answer, but it is really the way we tackle the problem. Every time we make a technical decision, we ask ourselves if the way we’ve chosen makes sense from a power point of view.
Cadence: Having an integrated team covering all aspects of the design is a big plus.
Julien: Yes. While many NemeriX employees come from large companies, they often experienced the fact that the large size of a company can be a handicap for low-power design as communication between teams is not as easy as in a smaller structure. Being smaller and focused helps NemeriX have the necessary big-company processes in place, while also giving us the flexibility of small-company communication and execution. And since low power means to design something that is as “fit” as possible, it is very important not to over engineer your product.
Cadence: What is the value for you in using the Cadence Virtual CAD service program to support your design process?Julien: We tape out once every year or once every 18 months so each tapeout is a new process node for us. And, every new process node brings new challenges for the physical implementation. VCAD brings us the experience that would be very hard to acquire by ourselves. For example, when we went to 65nm with the design for manufacturability issues, we counted on VCAD to help solve the problems that are more linked to process.
VCAD leaves us with the opportunity to focus on our core competencies—low power GPS—in which we can add value. We use VCAD as a sort of shortcut. We save time, and it adds a lot of confidence to our design.
Cadence: What node are you working at now?
Julien: We used VCAD for 130nm, for 90nm and, now, for 65nm.
Cadence: Can you briefly describe the flow and tools that you use today for design and signoff?Julien: We are a fully Cadence-based company, both on the RF and digital design. For digital design, we are using a flow based mainly on RTL compiler and SoC Encounter®. VCAD is in charge of the sign-off part.
We split the back-end flow into two parts. The first part, which is usually until the clock implementation, is handled by NemeriX. The part after the clock tree implementation is handled by VCAD. We also take advantage of VCAD services as consulting for the first part of the flow.
Cadence: Any comments on the low power flow within the Cadence tools?Julien: Our main concern in terms of power is dynamic power. Static power is a lower level of concern.
We spend a lot of time on the clock tree optimization through clock tree gating, through inter-region balancing, and this is where we rely on the Cadence® tools. Also, to make sure that at every step in the flow we are going in the right direction in terms of power optimization, we run a simple power analysis for which we usually use RTL Compiler. We noticed that it is very important to give as many inputs as possible to the power analysis tool. Toggling activity, for example, is a must but even an accurate back-annotation (instead of parasitic estimation) can make a significant difference.
If you do not put the right level of information in your power analysis, you can get results that are completely misleading. This is something that we really insist on—getting reliable power analysis all along the flow. It helps us understand if we have made the right move and that we have optimized the right points.
In terms of the other methods, we are also using on-chip voltage regulation and power switch off. For our type of design and the constraints we have, we are not using multi-supply voltage. When we introduce a low power technique, we need to make sure it is truly bringing value and not only overhead with no gain. We keep the chips as small and efficient as possible
Cadence: Would you use the Common Power Format flow again in your designs?
Julian: Yes. Basically, the CPF-based flow has optimized a lot of manual steps that were introducing risk in the design. Also, all the verification methodology that is built around CPF with Conformal Low Power, for example, has brought a lot of confidence.
Cadence: Thank you for your time. It sounds like you this is an exciting time for you.
Julien: Yes, great company, great technical field and great team—and, we are just 40 minutes away from the ski slopes!Julien Buros Biography
Julien Buros, digital design team lead, has been with NemeriX since 2002. Before that he worked at ST Microelectronics in the RnD CAD group. Julien received his engineering degree and master thesis in the Polytechnic Institute of Grenoble.