PCI-SIG has (FINALLY) released the PCIe 4.0 rev 0.3 specification for members'
review, just in time for the annual Developer Conference at Santa Clara, CA, next week (June 4-5).
The Gen4 spec was announced 2.5 years ago with the 'usual'
objective - doubling the bandwidth while keeping backward compatibility. Sounds
easy, doesn't it? Well - the time it took to get to rev 0.3 hints that it's not a
So, what are the main changes/additions of the new spec?
- Speed negotiation and operation at 16.0 GT/s
- Link equalization procedure for 16.0 GT/s
- Inferring electrical idle conditions at 16.0 GT/s
- Reorganization of the PCI Express electrical
- Incorporation of all post Gen3 ECNs (including M-PCIe)
Cadence PCIe 4.0 VIP (announced last
month) provides support for all of those changes. The VIP will be demonstrated next week at
Cadence booth 9 at the Santa Clara Convention Center.
If you’re around, and curious about
M-PCIe verification, don't miss Mukul's paper - "Testing and Verification of M-PCIe Devices," on Wednesday, June 4, from 2:00-3:00pm (track 4, session 4).
See you next week!