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PCIe Gen4 LIVE Demo at PCI-SIG DevCon Next Week

Comments(0)Filed under: IP, VIP, PCI Express 3.0, Gen3, PCI-SIG, PCIe, PCIe Gen3, M-PCIe, Verification IP, NVMe, MPCIe

The PCI-SIG has (FINALLY) released the PCIe 4.0 rev 0.3 specification for members' review, just in time for the annual Developer Conference at Santa Clara, CA, next week (June 4-5).

The Gen4 spec was announced 2.5 years ago with the 'usual' objective - doubling the bandwidth while keeping backward compatibility. Sounds easy, doesn't it? Well - the time it took to get to rev 0.3 hints that it's not a trivial task. 

So, what are the main changes/additions of the new spec?

  1. Speed negotiation and operation at 16.0 GT/s
  2. Link equalization procedure for 16.0 GT/s
  3. Inferring electrical idle conditions at 16.0 GT/s
  4. Reorganization of the PCI Express electrical specification 
  5. Incorporation of all post Gen3 ECNs (including M-PCIe)

Cadence PCIe 4.0 VIP (announced last month) provides support for all of those changes. The VIP will be demonstrated next week at Cadence booth 9 at the Santa Clara Convention Center.

If you’re around, and curious about M-PCIe verification, don't miss Mukul's paper - "Testing and Verification of M-PCIe Devices," on Wednesday, June 4, from 2:00-3:00pm (track 4, session 4). 

See you next week!



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