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Intel Developer Forum (IDF13): A "Look Inside" the Technology Showcase

Comments(1)Filed under: Design IP, IP, Gen3, PCI Express, PCIe, MIPI, Cadence, Intel, M-PCIe, Arif Khan, Mahesh Wagh, IDF13, Intel Developer Forum, interoperability, Rajkumar Chandrashekhar, MPCIe

The recent Intel Developer Forum 2013 in San Francisco was notable for the sheer number of attendees and the broad spectrum of the technology industry they represented.

Intel's embrace of a more diversified computing ecosystem was on display -- Android mascots, tablets, and phones, and yes, servers and cloud software. Intel led the PC revolution with its x86 family of processors, but faces intense competition in the handheld space where low power competitors hold sway. The keynote speeches and technical sessions were rich in content. Topics ranged from the Quark family of SoCs to Moore's Law and Big Data, and everything in between.

On Day 1, new Intel CEO Brian Krzanich talked about the evolution from a CPU based architecture to an SoC based architecture. Renee James, Intel President, discussed integrated computing and the impact on daily tasks and our lifestyle. The second day covered topics on Mobility, a key area of focus for Intel as it attempts to gain share in the handheld, mobile, and wearable computing market.

While the days were packed with technical talks on all kinds of topics from HTML5 and Hadoop to overclocking for high performance gaming and content creation, the technology showcase was a reflection of the technology ecosystem. The show floor was grouped into regions (NVM Express, Superspeed USB, etc). 


Cadence booth at IDF13 manned by Rajkumar Chandrashekhar, Engineering Director 

Sponsors and exhibitors showcased everything from malware detection (Intel's McAfee) to instrumentation (LeCroy). Team Cadence was present in full force, with booth coverage from Bangalore, Austin, and San Jose! The piece de resistance at out booth was an interoperability demo of Cadence's MPCIe controller and MPHY, interoperating with Intel's MPCIe controller. The Intel and Cadence team had collaborated over the summer to make this happen. (This was the next step forward from our last demo at MIPI Allliance meeting and PCI SIG Devcon in June). Intel's Mahesh Wagh, lead author of the M-PCIe specification, conducted a technical session on the topic in the High Speed Peripherals track. His presentation can be found here SF13_HSTS003_100.pdf.

The event was an opportunity for Cadence and Intel to show a working demonstration of the new standard to ecosystem partners and customers. Visitors were impressed with the working combination of controller and M-PHY. Cadence's M-PHY has been used in many deployments in SoCs and application boards using the M-PHY have been used across the industry to verify a wide range of MIPI controllers. Interestingly, at the event, Cadence's M-PHY was spotted at an SSIC demo in an unrelated booth!

IDF continues to be a testament to the diversity of the technology industry and how Intel and other companies are collaborating with each other, where roles are at times fungible, changing from partner to customer to competitor. We can't wait to see some of the announcements from IDF13 become reality! 

Arif Khan 


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