will be under maintenance from Friday, Oct. 3rd at 6pm (PST) thru Sunday, Oct 5th at 11pm (PST). login, registration, community posting and commenting functionalities will be disabled.
Home > Community > Blogs > Design IP and Verification IP > ieee 802 3 working to standardize the next generation of ethernet phys
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence IP blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

IEEE 802.3 -- Standardizing the Next Generation of Ethernet PHYs

Comments(1)Filed under: Design IP, PHY, semiconductor IP, Ethernet, 802.3bs, Automotive Ethernet, Ethernet PHYs, IEEE 802.3, Marris, 400Gpbs, 40Gbps, data centers, 100Gbps

I attended the IEEE 802.3 standards meeting in York, England recently. Over 200 people came from all over the world to work on standards for the next generation of Ethernet products.

Work is ongoing to standardize new Ethernet PHYs (physical layer devices) for speeds of 1Gbps, 40Gbps, 100Gbps and 400Gbps. The 1Gbps work is focused on the automotive and industrial market segments, a field that Cadence is particularly committed to supporting with its Ethernet IP.

Ethernet is expected to be widely adopted in cars -- it meets all the speed, cost, reliability and inter-operability requirements. The IEEE working group is working to standardize a gigabit PHY optimized for automotive environments that will operate over a single twisted pair of copper. This is a speed upgrade to the existing 100M automotive PHY available from Broadcom. There is also consideration being given to start a project to standardize a method of pre-emption to allow time critical traffic to be sent for closed loop control. Pre-emption is something that manufacturers of industrial control systems are asking for, and is also of interest to the automotive market.

For 40Gbps, work is ongoing to standardize a PHY for operation over 30 meters of four-pair, balanced twisted-pair copper cabling (802.3bq project). The target application for this is data centers.

For 100Gbps, work is ongoing to standardize chip-to-chip and chip-to-module interfaces, backplane PHYs, a twin-ax PHY and a new lower cost multi-mode optical fibre PHY (802.3bj and 802.3bm projects). All these use four lanes operating at 25 Gbps per lane.

There is agreement on the specification for the chip-to-module interface but there is still a discussion over what the CAUI4 chip-to-chip specification will be. Implementers want to limit the loss budget of this to 15dB so the receiver's DFE can be eliminated to save power and reduce burst errors which affect CRC performance. However, some system providers would like a higher loss budget to allow a longer reach.

For 400Gbps, a study group is looking at what the objective should be for the yet to be formed 802.3bs task force. There seems to be agreement that the initial deployments will be sixteen lanes of 25 Gbps per lane and that the 802.3bs project will develop standards for a chip-to-module, a PHY for single-mode optical fibre and a PHY for multi-mode optical fiber.

Arthur Marris, September 2013.



Leave a Comment

E-mail (will not be published)
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.