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M-PCIe—The New Big Thing from MIPI Alliance and PCI-SIG

Comments(0)Filed under: Design IP, SoC Realization, controller IP, IP, SoC, PCI, PCI-SIG, future of IP, Jacek Duda, MIPI, Warsaw, MIPI Alliance, M-PHY, Cadence, Controller, PHY, Intel, M-PCIe, PCI Developers Conference, 2013, semiconductor IP, Arif Khan

If you’re reading this, you must have heard about the M-PCIe specification that has just been announced by two very important standardization bodies in the semiconductor industry—MIPI Alliance and PCI-SIG. According to the press release that was released during the PCI-SIG event last month, “M-PCIe specification provides uncompromised scalable performance while delivering a consistent user experience across multiple mobile platforms.” This sounds very appealing, but exactly does it mean to the mobile SoC developers?

As I wrote in my previous post, the MIPI Alliance is known for the introduction of over 30 specifications targeted for mobile platforms, and has managed to do this in just 10 years. Certainly, 10 years is a lot of time, and mobile market is the fastest growing segment of the semiconductor industry, but still the number is impressive. Even more impressive is the fact that these specs have been adopted by the major players in the market, and thus have made their way into pretty much every mobile device there is.

PCI-SIG, on the other hand, is very conservative when it comes to giving birth to a new child. Actually, they have been active for twice as long as MIPI and developed 10 times fewer specifications than their latest partner. But don’t let this unfavorable comparison fool you. The money in the PCI business is still far more than in the all MIPI Alliance specifications combined, mostly thanks to the wide adoption of the PCI, and later PCI Express bus in the infrastructure, storage, and PC markets.

This clash of the titans of their domains sends a very important message to the whole semiconductor market. It shows how much convergence there is between mobile and infrastructure, and the direction is now to take advantage of this fact. Actually, key players in both markets have been observing each other for quite some time, and actions have already been taken. ARM and Intel are perfect examples here, with ARM’s A57 targeted also for server architecture and Intel’s Atom processors implemented in mobile devices. While there is little chance of these two joining forces, there also are no obstacles for the standardization bodies coming from different worlds to create a synergy effect.

World premiere of the first native M-PCIe controller by Cadence at the MIPI Alliance event on 18 June.

For design IP providers, M-PCIe is a perfect opportunity to deliver to market a solution that has the best of both worlds, and to become ambassadors for the new technology. It’s no secret Intel is the founding father of the PCI architecture, and Qualcomm keeps the MIPI Alliance going strong.

Design IP leaders like Cadence and Synopsys already have solutions on M-PCIe. Cadence showed their demo on 18 June, at the MIPI Alliance Demo Day in Warsaw, Poland, while Synopsys demonstrated the IP a week later, at the PCI-SIG conference. This sequence actually makes Cadence the first company to reveal a working M-PCIe solution, and contrasts with the statement made by other IP providers recently. Also, I’ve just learned that only the Cadence solution is a native M-PCIe controller that runs without any “regular” PCI conversion layers in between.

Martin James of Cadence at the PCI-SIG Developers Conference, where M-PCIe was announced.

Altogether, the engagement from the standardization bodies, major chip manufacturing companies, and design IP leaders makes the M-PCIe the standard to watch. For SoC companies, M-PCIe is definitely something that they want to give a thought to before they leave for well-deserved holidays. Definitely better before than after.


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