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Cadence First to Demo Complete M-PCIe PHY and Controller Solution at MIPI and PCI-SIG Conferences

Comments(1)Filed under: Design IP, IP, Gen3, PCI, PCI Express, PCIe, MIPI, M-PHY, Cadence, PMC, Controller, PHY, Intel, LeCroy, M-PCIe, DevCon, PCI Developers Conference, 2013, semiconductor IP, Arif Khan
One of the hottest (or should I say coolest – because low power is so important) new standards is PCI Express® (PCIe) over M-PHY, or M-PCIe.  To implement it properly, it’s essential that the controller and PHY work well together as the interface specification between them is, to put it mildly, loosely defined.  

We just finished the PCI-SIG 2013 conference at the Santa Clara Convention Center, and our M-PCIe demo was a big hit.  We actually demoed it for the first time the week of June 17, 2013, at the MIPI Alliance’s European Meeting in Warsaw.

Visitors throng to Cadence's M-PCIe Demo at PCI SIG, Santa Clara, 2013. Martin James of Cadence answers questions.

It was fitting that Cadence would be the first to demonstrate the PHY and controller IP with high-speed links across M-PHYs. Cadence was one of the initial sponsors of this ECN. The Cadence design team actively participated in the discussions and contributed to the specification. Our design is a native RMMI based implementation, unlike implementations that convert PCIe to M-PCIe using a shim layer. The shortcut via the shim might be tempting, but does not help realize the power advantages of the protocol!

Three separate presentations on M-PCIe at the DevCon indicate the significance of this update. Mahesh Wagh of Intel, author of the specification, delivered one of the talks to a standing room only audience.  Gary Dick, Cadence M-PCIe Architect presented a case study (link available to PCI SIG members only) on Cadence’s M-PCIe implementation. His wry Scottish humor kept the audience in splits as he worked his way through the complexities of clock tolerance compensation and nitty-gritty of formal verification techniques to guarantee robustness of LTSSM design!  

The PCI SIG Developers Conference is the signature event for all things in the world of PCI Express. This year’s event at the Santa Clara Convention Center brought developers, integrators, and implementers under one roof to talk about current topics and future developments for this key interconnect used in a plethora of system designs. The DevCon is a conference by engineers, for engineers, and is one of the few trade shows where the exhibit floor is chock-a-block with gadgetry.

Last September, the PCI SIG and MIPI Alliance announced a collaboration to define PCIe over MIPI M-PHY (M-PCIe). M-PCIe brings additional low-power capabilities to systems and extends the reach of the protocol into mobile platforms, including ultra-thin and light devices. Many mobile platforms already use an M-PHY for other MIPI protocols, and M-PCIe allows these systems to use the scalable PCIe architecture to add lanes as bandwidths change across platforms. 

The other topics of interest at the DevCon were the Gen4 talks (doubling the speed from Gen3 to 16GT/s). The Gen4 ECN draft is still in the sub-committees and will take some time to mature. The PCI SIG also introduced the M.2 form factor formally at the event.

The current Gen3 systems continue to generate excitement as their use is become more widespread in storage systems and network flow engines. One of the star attractions here was the Cadence Gen3 IP demo, showcasing a customer implementation using our PCIe Controller IP to build a PCIe to SAS solution. We built a demo using off-the-shelf components (SAS SSD drives, standard motherboard) to show an IOMeter traffic demo. The Cadence Gen3 controller showed 95% link utilization under sustained traffic conditions. Teledyne-LeCroy partnered with us to provide protocol analyzer support (and independent cross-check of our performance numbers).

Cadence PCIe Team (Osman Javed, Arif Khan, and Gary Dick) with Wei Wang (Cadence Sigrity Group) with the Gen3 Performance Demo

The Cadence booth also had presence from our Sigrity product line and Verification IP team, representing the broad presence in this arena. Guoqing Zhang of Cadence also presented a talk on testing and verification of NVMe PCIe Devices. 


The wide variety of exhibitors and talks made for a particularly interesting conference. Games, drawings, and free food kept the attendees entertained. As the day ended, the music played “Tonight’s gonna be a good night!” After a great conference day, that would be a tough act to follow!
 

The Cadence booth at PCI SIG Developers Conference 2013: Center Stage 

Arif Khan

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