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Video, Part 2: Cadence Demonstrates PCIe Gen3 Advanced Features

Comments(0)Filed under: Design IP, controller IP, IP, PCI Express 3.0, Gen3, video, PCI Express, PCIe, SR-IOV, PCIe Gen3

Welcome back for Part 2 of a two-part PCI-SIG video demo featuring Cadence’s PCI Express Gen3 Controller IP advanced capabilities, with a discussion on Single Root I/O Virtualization (SR-IOV). Part 1 was covered in a recent blog post.

What is SR-IOV? Briefly, SR-IOV is a specification that allows a PCIe device to appear to be multiple separate physical PCIe devices. PCI-SIG created and maintains the SR-IOV specification with the goal of having a standard specification to help promote interoperability. One of the milestones achieved for Cadence’s design IP for PCI Express Gen3 is proving SR-IOV interoperability in silicon against an Intel chipset.

Why is it important? The two main advantages of an SR-IOV PCIe device are:

  • It allows multiple OS’s to have their own private view of the PCIe device
  • It helps improve I/O performance by reducing  latency of the hypervisor
How have Cadence customers used PCI Express Gen3 SR-IOV to solve their design problems? In one example, a SAS RAID controller using 2 physical functions (PFs) and 16 virtual functions (VFs) was able to have 16 guest applications privately access the PCIe device. VFs are “lightweight” and have the advantage of requiring significantly less logic overhead than PFs. 

Please see the video below for more details. Also, please comment on how you've seen PCIe Gen3 SR-IOV used in different applications.


Stella Murphy



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