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New Memory Technologies, New Possibilities

Comments(0)Filed under: Wide-IO, DDR4, memory, DDR, Design IP, storage, SoC Realization, Denali, controller IP, IP, SoC, wide I/O

As a complete gadget geek, it’s always exciting to play with the latest technological toys. But if you stop to consider how each new wave of applications powered by these devices impacts the underlying SoC designs, you quickly realize that the memory and storage subsystem is now central to SoC Realization. Poor memory and storage design will impact everything from the user experience to the applications that are possible. There is nothing quite so sad as a shiny new gadget that falls short because of poor memory performance (something easily avoided with the right IP), or trying to install a new app only to have to decide what you must delete to make room for it.

It’s been a busy few weeks for the IP team with the announcement of support for two new memory technologies – DDR4 and Wide I/O.

With Wide I/O and DDR4 offering significantly improvements for the device classes they target for, it’s exciting to contemplate how design teams will leverage them to deliver on the next wave of devices. So whether it’s a high performance gaming desktop, a sleek new tablet, or enterprise equipment that interests you, new memory technologies will play a key role.

Learn more about Cadence Design IP for Memory and Storage.

Neil Hand

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